Swagata Mandal

Orcid: 0000-0002-0534-3083

According to our database1, Swagata Mandal authored at least 16 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture.
CoRR, 2022

2021
Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform.
IEEE Trans. Aerosp. Electron. Syst., 2021

2019
Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

iMACE: In-Memory Acceleration of Classic McEliece Encoder.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
ReRAM Based In-Memory Computation of Single Bit Error Correcting BCH Code.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

ReRAM-based In-Memory Computation of Galois Field arithmetic.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Lightweight ASIC Implementation of AEGIS-128.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

2017
Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware.
Microprocess. Microsystems, 2017

2016
A Novel Method for Soft Error Mitigation in FPGA Using Modified Matrix Code.
IEEE Embed. Syst. Lett., 2016

2015
Outage Minimized Joint Power and Channel Allocation in Multihop Cognitive Radio Networks: A Lifetime-Centric Approach.
Wirel. Pers. Commun., 2015

High speed fault tolerant secure communication for muon chamber using fpga based gbt emulator.
CoRR, 2015

FPGA based High Speed Data Acquisition System for High Energy Physics Application.
CoRR, 2015

A Novel Method for Soft Error Mitigation in FPGA using Adaptive Cross Parity Code.
CoRR, 2015

FPGA Based Novel High Speed DAQ System Design with Error Correction.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

FPGA Implementation of High Speed Latency Optimized Optical Communication System Based on Orthogonal Concatenated Code.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2013
Joint power and channel allocation for outage probability minimization in cognitive radio ad hoc networks.
Proceedings of the Fifth International Conference on Communication Systems and Networks, 2013


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