Parisa Razaghi

According to our database, Parisa Razaghi authored at least 6 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Host-Compiled Multicore System Simulation for Early Real-Time Performance Evaluation.

Parisa Razaghi, Andreas Gerstlauer

ACM Trans. Embed. Comput. Syst., 2014

2012

Predictive OS Modeling for Host-Compiled Simulation of Periodic Real-Time Task Sets.

Parisa Razaghi, Andreas Gerstlauer

IEEE Embed. Syst. Lett., 2012

Automatic timing granularity adjustment for host-compiled software simulation.

Parisa Razaghi, Andreas Gerstlauer

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Abstract system-level models for early performance and power exploration.

Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Host-compiled multicore RTOS simulator for embedded real-time software development.

Parisa Razaghi, Andreas Gerstlauer

Proceedings of the Design, Automation and Test in Europe, 2011

2007

A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.

Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the Forum on specification and Design Languages, 2007