Zainalabedin Navabi

According to our database, Zainalabedin Navabi authored at least 204 papers between 1979 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs.

Nooshin Nosrati, Zainalabedin Navabi

IEEE Access, 2024

2023

HIRMA: High-Performance Implementation for RISC-V Microcontroller Applications.

Negin Safari, Amirmahdi Joudi, Maryam Rajabalipanah, Zahra Jahanpeima, Hasan Sadeghzadeh, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2023

Multi-Level Fault Injection Methodology Using UVM-SystemC.

Ebrahim Nouri, Nooshin Nosrati, Hanieh Totonchi Asl, Mozhgan Rezaie Manavand, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2023

Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction.

Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad-Javad Zare, Zainalabedin Navabi

Proceedings of the IEEE European Test Symposium, 2023

A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators.

Nooshin Nosrati, Zainalabedin Navabi

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

A Low-Cost Combinational Approximate Multiplier.

Zahra Hojati, Zainalabedin Navabi

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

Testable Array Multipliers for a Better Utilization of C-Testability and Bijectivity.

Fatemeh Sheikh Shoaei, Alireza Nahvy, Zainalabedin Navabi

CoRR, 2022

A Secure Canary-Based Hardware Approach Against ROP.

Mahboobe Sadeghipour Roodsari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the Italian Conference on Cybersecurity (ITASEC 2022), 2022

MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors.

Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

Concurrent Error Detection for LSTM Accelerators.

Nooshin Nosrati, Seyedeh Maryam Ghasemi, Mahboobe Sadeghipour Roodsari, Zainalabedin Navabi

Proceedings of the IEEE European Test Symposium, 2022

2021

n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator.

Mahboobe Sadeghipour Roodsari, Hanieh Totonchi Asl, Zainalabedin Navabi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Integrating an Interconnect BIST with Crosstalk Avoidance Hardware.

Mahsa Akhsham, Zainalabedin Navabi

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

AFTAB: A RISC-V Implementation with Configurable Gateways for Security.

Maryam Rajabalipanah, Mahboobe Sadeghipour Roodsari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2021

Online Testing of a Row-Stationary Convolution Accelerator.

Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi

Proceedings of the 26th IEEE European Test Symposium, 2021

Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester.

Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

2020

Self-Adjusting Monitor for Measuring Aging Rate and Advancement.

Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi

IEEE Trans. Emerg. Top. Comput., 2020

Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information.

Mohammad Ebrahimi, Zainalabedin Navabi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs.

Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi

IEEE Trans. Computers, 2020

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links.

Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Built-In Predictors for Dynamic Crosstalk Avoidance.

Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the IEEE European Test Symposium, 2020

Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator.

Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Zainalabedin Navabi

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation.

Mahboobe Sadeghipour Roodsari, Mohamad Ali Saber, Zainalabedin Navabi

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

An ESL Environment for Modeling Electrical Interconnect Faults.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

SCOAP-based Directed Random Test Generation for Combinational Circuits.

Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization.

Samira Ahmadi Farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.

Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi

Proceedings of the 24th IEEE European Test Symposium, 2019

Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme.

Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi

Proceedings of the 24th IEEE European Test Symposium, 2019

2018

Automatic Correction of Dynamic Power Management Architecture in Modern Processors.

Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi

IEEE Trans. Very Large Scale Integr. Syst., 2018

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.

Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi

IEEE Trans. Very Large Scale Integr. Syst., 2018

Near-Optimal Node Selection Procedure for Aging Monitor Placement.

Somayeh Sadeghi Kohan, Arash Vafaei, Zainalabedin Navabi

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.

Ramin Rezaeizadeh Rookerd, Somayeh Sadeghi Kohan, Zainalabedin Navabi

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017

Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.

Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi

IEEE Trans. Very Large Scale Integr. Syst., 2017

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.

Zana Ghaderi, Mohammad Ebrahimi, Zainalabedin Navabi, Eli Bozorgzadeh, Nader Bagherzadeh

IEEE Trans. Computers, 2017

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint.

Elaheh Sadredini, Mohammad Hashem Haghbayan, Mahmood Fathy, Zainalabedin Navabi

CoRR, 2017

BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding.

Elaheh Sadredini, Mohammadreza Najafi, Mahmood Fathy, Zainalabedin Navabi

CoRR, 2017

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach.

Hossein Sabaghian Bidgoli, Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A novel SAT-based ATPG approach for transition delay faults.

Farzaneh Zokaee, Hossein Sabaghian Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi

Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems.

Rasool Sharifi, Zainalabedin Navabi

Proceedings of the 22nd IEEE European Test Symposium, 2017

TruncApp: A truncation-based approximate divider for energy efficient DSP applications.

Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram, Zainalabedin Navabi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Self-Healing Many-Core Architecture: Analysis and Evaluation.

Arezoo Kamran, Zainalabedin Navabi

VLSI Design, 2016

Stochastic testing of processing cores in a many-core architecture.

Arezoo Kamran, Zainalabedin Navabi

Integr., 2016

Optimistic clock adjustment for preventing Better-than-worst-case violations.

Seyedeh Hanieh Hashemi, Reza Namazian, Zainalabedin Navabi

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping.

Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

An improved scheme for pre-computed patterns in core-based SoC architecture.

Elaheh Sadredini, Reza Rahimi, Paniz Foroutan, Mahmood Fathy, Zainalabedin Navabi

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Universal mitigation of NBTI-induced aging by design randomization.

Maksim Jenihhin, Alexander Kamkin, Zainalabedin Navabi, Somayeh Sadeghi Kohan

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

ESL design with RTL-verified predesigned abstract communication channels.

Hamed Najafi Haghi, Mikhail M. Chupilko, Alexander S. Kamkin, Zainalabedin Navabi

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Path selection and sensor insertion flow for age monitoring in FPGAs.

Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zain Navabi

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition.

Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

IEEE Trans. Computers, 2015

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.

Mohammad Ansari, Hassan Afzali-Kusha, Behzad Ebrahimi, Zainalabedin Navabi, Ali Afzali-Kusha, Massoud Pedram

Integr., 2015

System-level assertions: approach for electronic system-level verification.

Hasan Sohofi, Zainalabedin Navabi

IET Comput. Digit. Tech., 2015

Signature oriented model pruning to facilitate multi-threaded processors debugging.

Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model.

Elmira Karimi, Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mahmoud Tabandeh, Pasi Liljeberg, Zainalabedin Navabi

Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Low power scheduling in high-level synthesis using dual-Vth library.

Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation.

Somayeh Sadeghi Kohan, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Multi-valued logic test access mechanism for test time and power reduction.

Amirreza Nekooei, Zainalabedin Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

HDLs evolve as they affect design methodology for a higher abstraction and a better integration.

Zainalabedin Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Online self adjusting progressive age monitoring of timing variations.

Somayeh Sadeghi Kohan, Mehdi Kamal, John McNeil, Paolo Prinetto, Zain Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Utilizing NOPs for online deterministic testing of simple processing cores.

Rasoul Jafari, Elham Zahraei Salehi, Zain Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Application-specific power-aware mapping for reconfigurable NoC architectures.

Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Power-aware online testing of manycore systems in the dark silicon era.

Mohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi, Hannu Tenhunen

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

High-level design space exploration of locally linear neuro-fuzzy models for embedded systems.

Mohammadreza Baharani, Hamid Noori, Mohammad Aliasgari, Zain Navabi

Fuzzy Sets Syst., 2014

Configurable Systolic Matrix Multiplication.

Parastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Back-annotation of gate-level power properties into system level descriptions.

Najmeh Farajipour Ghohroud, Zainalabedin Navabi

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.

Farimah Farahmandi, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Assertion-based verification for system-level designs.

Hasan Sohofi, Zainalabedin Navabi

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

RTL datapath optimization using system-level transformations.

Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An off-line MDSI interconnect BIST incorporated in BS 1149.1.

Marzieh Mohammadi, Somayeh Sadeghi Kohan, Nasser Masoumi, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

Improving polynomial datapath debugging with HEDs.

Somayeh Sadeghi Kohan, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

Homogeneous many-core processor system test distribution and execution mechanism.

Arezoo Kamran, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

Automatic correction of certain design errors using mutation technique.

Payman Behnam, Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 19th IEEE European Test Symposium, 2014

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure.

Shahrzad Keshavarz, Amirreza Nekooei, Zainalabedin Navabi

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A heuristic path selection method for small delay defects test.

Paniz Foroutan, Mehdi Kamal, Zainalabedin Navabi

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013

A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits.

Mohammad Mirzaei, Mahmoud Tabandeh, Bijan Alizadeh, Zainalabedin Navabi

IEEE Des. Test, 2013

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.

Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Online periodic test mechanism for homogeneous many-core processors.

Arezoo Kamran, Zainalabedin Navabi

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A new structure for interconnect offline testing.

Somayeh Sadeghi Kohan, Shahrzad Keshavarz, Farzaneh Zokaee, Farimah Farahmandi, Zainalabedin Navabi

Proceedings of the East-West Design & Test Symposium, 2013

Extracting complete set of equations to analyze VHDL-AMS descriptions.

Arezoo Kamran, Vahid Janfaza, Zainalabedin Navabi

Proceedings of the East-West Design & Test Symposium, 2013

A probabilistic approach for counterexample generation to aid design debugging.

Payman Behnam, Hossein Sabaghian Bidgoli, Bijan Alizadeh, Kamyar Mohajerani, Zainalabedin Navabi

Proceedings of the East-West Design & Test Symposium, 2013

2012

Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2^m and algebraic techniques.

Samaneh Ghandali, Bijan Alizadeh, Zainalabedin Navabi, Masahiro Fujita

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

BS 1149.1 extensions for an online interconnect fault detection and recovery.

Somayeh Sadeghi Kohan, Majid Namaki-Shoushtari, Fatemeh Javaheri, Zainalabedin Navabi

Proceedings of the 2012 IEEE International Test Conference, 2012

A novel graceful degradable routing algorithm for 3D on-chip networks.

Reza Nakhjavani, Ali Shahabi, Saeed Safari, Zainalabedin Navabi

Proceedings of the 2012 Interconnection Network Architecture, 2012

Soft Error Analysis on Communication Channels in On-Chip Communication Networks.

Mohammadreza Najafi, Saeed Safari, Zainalabedin Navabi

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Effective RT-level software-based self-testing of embedded processor cores.

Parisa Kabiri, Zainalabedin Navabi

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST.

M. H. Haghbayan, Saeed Safari, Zainalabedin Navabi

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

A Probabilistic and Constraint Based Approach for Low Power Test Generation.

Hossein Sabaghian Bidgoli, Majid Namaki-Shoushtari, Zainalabedin Navabi

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Configurable architecture for memory BIST.

Atieh Lotfi, Parisa Kabiri, Zainalabedin Navabi

Proceedings of the 9th East-West Design & Test Symposium, 2011

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing.

Nastaran Nemati, Zainalabedin Navabi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Online Test Macro Scheduling and Assignment in MPSoC Design.

Behnam Khodabandeloo, Seyyed Alireza Hoseini, Sajjad Taheri, Mohammad Hashem Haghbayan, Mahmood Reza Babaei, Zainalabedin Navabi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.

Fatemeh Javaheri, Majid Namaki-Shoushtari, Parastoo Kamranfar, Zainalabedin Navabi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Real-time embedded emotional controller.

Mohammad Reza Jamali, Masood Deh-Yadegari, Arash Arami, Caro Lucas, Zainalabedin Navabi

Neural Comput. Appl., 2010

EDXY - A low cost congestion-aware routing algorithm for network-on-chips.

Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, Zainalabedin Navabi

J. Syst. Archit., 2010

Using context based methods for test data compression.

Sara Karamati, Zainalabedin Navabi

Proceedings of the 2011 IEEE International Test Conference, 2010

Automatic selection of efficient observability points in combinational gate level circuits using particle swarm optimization.

Amirali Ghofrani, Fatemeh Javaheri, Saeed Safari, Zainalabedin Navabi

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

A partitioning approach to improve reconfigurable neuron-inspired online BIST.

Ali Shahabi, S. Behdad Hosseini, Hasan Sohofi, Zainalabedin Navabi

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Near optimal machine learning based random test generation.

Niki Shakeri, Nastaran Nemati, Majid Nili Ahmadabadi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Low cost error tolerant motion estimation for H.264/AVC standard.

M. H. Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

A mixed HDL/PLI test package.

Nastaran Nemati, Majid Namaki-Shoushtari, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Virtual tester development using HDL/PLI.

Arezoo Kamran, Nastaran Nemati, Somayeh Sadeghi Kohan, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Merit based directed random test generation (MDRTG) scheme for combinational circuits.

Arezoo Kamran, Mohammad Saeed Jahangiry, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

ESL design methodology for architecture exploration.

Fatemeh Javaheri, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Generating test patterns for sequential circuits using random patterns by PLI functions.

Mohammad Hashem Haghbayan, Alireza Yazdanpanah, Sara Karamati, Ramyar Saeedi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Architecture design and technical methodology for bus testing.

M. H. Haghbayan, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Assertion based verification in TLM.

Amirali Ghofrani, Fatemeh Javaheri, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

A TLM2.0 assertion library with centralized monitoring approach.

Amirali Ghofrani, Sheis Abolma'ali, Zahra Najafi Haghi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Facilitating testability of TLM FIFO: SystemC implementations.

Homa Alemzadeh, Marco Cimei, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

Code optimization for enhancing SystemC simulation time.

Homa Alemzadeh, Soheil Aminzadeh, Reihaneh Saberi, Zainalabedin Navabi

Proceedings of the 2010 East-West Design & Test Symposium, 2010

A reconfigurable online BIST for combinational hardware using digital neural networks.

S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi

Proceedings of the 15th European Test Symposium, 2010

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment.

M. H. Haghbayan, Sara Karamati, Fatemeh Javaheri, Zainalabedin Navabi

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Sign Bit Reduction Encoding For Low Power Applications.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

J. Signal Process. Syst., 2009

Emotion on FPGA: Model driven approach.

Mohammad Reza Jamali, Arash Arami, Masood Deh-Yadegari, Caro Lucas, Zainalabedin Navabi

Expert Syst. Appl., 2009

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.

Nastaran Nemati, Amirhossein Simjour, Amirali Ghofrani, Zainalabedin Navabi

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

A Selective Trigger Scan Architecture for VLSI Testing.

Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi

IEEE Trans. Computers, 2008

Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults.

Naghmeh Karimi, Armin Alaghi, Mahshid Sedghi, Zainalabedin Navabi

J. Univers. Comput. Sci., 2008

An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.

Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Stall Power Reduction in Pipelined Architecture Processors.

Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Enhanced TED: A New Data Structure for RTL Verification.

Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

"Plug & Test" at System Level via Testable TLM Primitives.

Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the 2008 IEEE International Test Conference, 2008

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure.

Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Zainalabedin Navabi

Proceedings of the 2008 IEEE International Test Conference, 2008

Reliability in Application Specific Mesh-Based NoC Architectures.

Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.

Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Functional testing approaches for "BIFST-able" tlm_fifo.

Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level.

Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

Automating Hardware/Software partitioning using dependency Graph.

Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

System level hardware design and simulation with SystemAda.

Negin Mahani, Parnian Mokri, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

An advanced method for synthesizing TLM2-based interfaces.

Nadereh Hatami, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

Utilizing HDL simulation engines for accelerating design and test processes.

Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

Reliable NoC architecture utilizing a robust rerouting algorithm.

Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi

Proceedings of the 2008 East-West Design & Test Symposium, 2008

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.

Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, Zainalabedin Navabi

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Low test application time resource binding for behavioral synthesis.

Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi

ACM Trans. Design Autom. Electr. Syst., 2007

Low overhead DFT using CDFG by modifying controller.

Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, Zainalabedin Navabi

IET Comput. Digit. Tech., 2007

Degradable mesh-based on-chip networks using programmable routing tables.

Ali Shahabi, Nima Honarmand, Hasan Sohofi, Zainalabedin Navabi

IEICE Electron. Express, 2007

A UML Based System Level Failure Rate Assessment Technique for SoC Designs.

Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

High Level Synthesis of Degradable ASICs Using Virtual Binding.

Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Programmable Routing Tables for Degradable Torus-Based Networks on Chips.

Ali Shahabi, Nima Honarmand, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New Approach for Design and Verification of Transaction Level Models.

Mohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.

Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

An Analytical Model for Reliability Evaluation of NoC Architectures.

Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

RT level reliability enhancement by constructing dynamic TMRS.

Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.

Parisa Razaghi, Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the Forum on specification and Design Languages, 2007

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.

Nima Honarmand, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi

Proceedings of the Forum on specification and Design Languages, 2007

On-Chip Verification of NoCs Using Assertion Processors.

Mohammad Reza Kakoee, Mohammad Hossein Neishaburi, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.

Armin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.

Mohammad Hossein Neishaburi, Mohammad Reza Kakoee, Masoud Daneshtalab, Saeed Safari, Zainalabedin Navabi

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Using the inter- and intra-switch regularity in NoC switch testing.

Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

An HDL-Based Platform for High Level NoC Switch Testing.

Mahshid Sedghi, Armin Alaghi, Elnaz Koopahi, Zainalabedin Navabi

Proceedings of the 16th Asian Test Symposium, 2007

Optimized Assignment Coverage Computation in Formal Verification of Digital Systems.

Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi

Proceedings of the 16th Asian Test Symposium, 2007

2006

Scan-Based Structure with Reduced Static and Dynamic Power Consumption.

Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi

J. Low Power Electron., 2006

A Test Approach for Look-Up Table Based FPGAs.

Ehsan Atoofian, Zainalabedin Navabi

J. Comput. Sci. Technol., 2006

ByZFAD: a low switching activity architecture for shift-and-add multipliers.

Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Ant colony based routing architecture for minimizing hot spots in NOCs.

Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

An Optimized BIST Architecture for FPGA Look-Up Table Testing.

Mahnaz Sadoughi Yarandi, Armin Alaghi, Zainalabedin Navabi

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A New Protocol Stack Model for Network on Chip.

Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Serial Bus Encoding for Low Power Application.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the International Symposium on System-on-Chip, 2006

Low-power and low-latency cluster topology for local traffic NoCs.

Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DCim++: a C++ library for object oriented hardware design and distributed simulation.

Hadi Esmaeilzadeh, A. Moghimi, Eiman Ebrahimi, Caro Lucas, Zainalabedin Navabi, A. M. Fakhraie

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A concurrent testing method for NoC switches.

Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

ESTA: An Efficient Method for Reliability Enhancement of RT-Level Designs.

Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the 15th Asian Test Symposium, 2006

An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing.

Armin Alaghi, Mahnaz Sadoughi Yarandi, Zainalabedin Navabi

Proceedings of the 15th Asian Test Symposium, 2006

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.

Masoud Daneshtalab, Ashkan Sobhani, Ali Afzali-Kusha, Omid Fatemi, Zainalabedin Navabi

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

Instruction-level test methodology for CPU core self-testing.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

ACM Trans. Design Autom. Electr. Syst., 2005

An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.

Hamid Reza Ghasemi, Zainalabedin Navabi

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Flow Graph Technique for DFT Controller Modification.

Mohammad Hosseinabady, Pejman Lotfi-Kamran, Pedram A. Riahi, Fabrizio Lombardi, Zainalabedin Navabi

Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.

Arash Hooshmand, Saeed Shamshiri, Mohammad Alisafaee, Bijan Alizadeh, Pejman Lotfi-Kamran, Mostafa Naderi, Zainalabedin Navabi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low-power scan-path architecture.

Mohammad Alisafaee, Safar Hatami, Ehsan Atoofian, Zainalabedin Navabi, Ali Afzali-Kusha

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Combination of Assertion and HSAT Methods For Automated Test Vectors Generation.

Mostafa Naderi, Zainalabedin Navabi

Proceedings of the Forum on specification and Design Languages, 2005

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Simultaneous Reduction of Dynamic and Static Power in Scan Structures.

Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi

Proceedings of the 2005 Design, 2005

Enhancing Fault Simulation Performance by Dynamic Fault Clustering.

Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.

Hadi Esmaeilzadeh, Saeed Shamshiri, Pooya Saeedi, Zainalabedin Navabi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

TED+: a data structure for microprocessor verification.

Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Digital design and implementation with field programmable devices.

Zainalabedin Navabi

Kluwer, ISBN: 978-1-4020-8011-1, 2005

2004

Using data compression in automatic test equipment for system-on-chip testing.

Farzin Karimi, Zainalabedin Navabi, Waleed Meleis, Fabrizio Lombardi

IEEE Trans. Instrum. Meas., 2004

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.

Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin

J. Electron. Test., 2004

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.

Zainalabedin Navabi, Shahrzad Mirkhani, Meisam Lavasani, Fabrizio Lombardi

J. Electron. Test., 2004

Using Integer Equations to Check PSL Properties in RT Level Design.

Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Instruction level test methodology for CPU core software-based self-testing.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.

Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Property Checking based on Hierarchical Integer Equations.

Bijan Alizadeh, Zainalabedin Navabi

Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003

Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.

Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi

Proceedings of the IFIP VLSI-SoC 2003, 2003

Processor Testing Using an ADL Description and Genetic Algorithms.

Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi

Proceedings of the IFIP VLSI-SoC 2003, 2003

A Low Power BIST Architecture for FPGA Look-Up Table Testing.

Ehsan Atoofian, Zainalabedin Navabi

Proceedings of the IFIP VLSI-SoC 2003, 2003

Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching.

Morteza Fayyazi, David R. Kaeli, Zainalabedin Navabi

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Utilizing Various ADL Facets for Instruction Level CPU Test.

Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.

Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the International Conference on Embedded Systems and Applications, 2003

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.

Pedram A. Riahi, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.

Ehsan Atoofian, Zainalabedin Navabi

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Data Compression for System-on-Chip Testing Using ATE.

Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.

Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

An efficient BIST method for testing of embedded SRAMs.

Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.

Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Fault Simulation for VHDL Based Test Bench and BIST Evaluation.

Hamed Farshbaf, Mina Zolfy, Shahrzad Mirkhani, Zainalabedin Navabi

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999

Hardware Description in Verilog.

Zainalabedin Navabi

Proceedings of the VLSI Handbook., 1999

1995

A Transistor Level Link for VHDL Simulation of VLSI Circuits.

Zainalabedin Navabi, Zahra Razavi

Simul., 1995

1993

Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.

Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai

Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992

A high-level language for design and modeling of hardware.

Zainalabedin Navabi

J. Syst. Softw., 1992

1991

Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions.

Zainalabedin Navabi, Mehran Massoumi

Simul., 1991

Compiling gate <i>RC</i> models into a top level simulation model for rough timing analysis of VLSI circuits.

Zainalabedin Navabi

Microprocess. Microsystems, 1991

1984

Hardware Compilation from an RTL to a Storage Logic Array Target.

Fredrick J. Hill, Zainalabedin Navabi, Chen H. Chiang, Duan-Ping Chen, Manzer Masud

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1981

Structure Specification with a Procedural Hardware Description Language.

Fredrick J. Hill, R. E. Swanson, Manzer Masud, Zainalabedin Navabi

IEEE Trans. Computers, 1981

1979

Efficient simulation of AHPL.

Zainalabedin Navabi, Fredrick J. Hill

Proceedings of the 16th Design Automation Conference, 1979