Zainalabedin Navabi

According to our database1, Zainalabedin Navabi authored at least 173 papers between 1979 and 2019.

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2019
An ESL Environment for Modeling Electrical Interconnect Faults.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

SCOAP-based Directed Random Test Generation for Combinational Circuits.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.
Proceedings of the 24th IEEE European Test Symposium, 2019

Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme.
Proceedings of the 24th IEEE European Test Symposium, 2019

2018
Automatic Correction of Dynamic Power Management Architecture in Modern Processors.
IEEE Trans. VLSI Syst., 2018

Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.
IEEE Trans. VLSI Syst., 2018

Near-Optimal Node Selection Procedure for Aging Monitor Placement.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

2017
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.
IEEE Trans. VLSI Syst., 2017

SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs.
IEEE Trans. Computers, 2017

Test Generation and Scheduling for a Hybrid BIST Considering Test Time and Power Constraint.
CoRR, 2017

BILBO-friendly Hybrid BIST Architecture with Asymmetric Polynomial Reseeding.
CoRR, 2017

Reducing Search Space for Fault Diagnosis: A Probability-Based Scoring Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A novel SAT-based ATPG approach for transition delay faults.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Online Profiling for cluster-specific variable rate refreshing in high-density DRAM systems.
Proceedings of the 22nd IEEE European Test Symposium, 2017

TruncApp: A truncation-based approximate divider for energy efficient DSP applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Self-Healing Many-Core Architecture: Analysis and Evaluation.
VLSI Design, 2016

Stochastic testing of processing cores in a many-core architecture.
Integr., 2016

Optimistic clock adjustment for preventing Better-than-worst-case violations.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

An improved scheme for pre-computed patterns in core-based SoC architecture.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Universal mitigation of NBTI-induced aging by design randomization.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

ESL design with RTL-verified predesigned abstract communication channels.
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016

Path selection and sensor insertion flow for age monitoring in FPGAs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition.
IEEE Trans. Computers, 2015

A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies.
Integr., 2015

System-level assertions: approach for electronic system-level verification.
IET Computers & Digital Techniques, 2015

Signature oriented model pruning to facilitate multi-threaded processors debugging.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Low power scheduling in high-level synthesis using dual-Vth library.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Multi-valued logic test access mechanism for test time and power reduction.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

HDLs evolve as they affect design methodology for a higher abstraction and a better integration.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Online self adjusting progressive age monitoring of timing variations.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Utilizing NOPs for online deterministic testing of simple processing cores.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Application-specific power-aware mapping for reconfigurable NoC architectures.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Power-aware online testing of manycore systems in the dark silicon era.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
High-level design space exploration of locally linear neuro-fuzzy models for embedded systems.
Fuzzy Sets Syst., 2014

Configurable Systolic Matrix Multiplication.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Back-annotation of gate-level power properties into system level descriptions.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Assertion-based verification for system-level designs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

RTL datapath optimization using system-level transformations.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

An off-line MDSI interconnect BIST incorporated in BS 1149.1.
Proceedings of the 19th IEEE European Test Symposium, 2014

Improving polynomial datapath debugging with HEDs.
Proceedings of the 19th IEEE European Test Symposium, 2014

Homogeneous many-core processor system test distribution and execution mechanism.
Proceedings of the 19th IEEE European Test Symposium, 2014

Automatic correction of certain design errors using mutation technique.
Proceedings of the 19th IEEE European Test Symposium, 2014

Preemptive multi-bit IJTAG testing with reconfigurable infrastructure.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

A heuristic path selection method for small delay defects test.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

2013
A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits.
IEEE Design & Test, 2013

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Online periodic test mechanism for homogeneous many-core processors.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A new structure for interconnect offline testing.
Proceedings of the East-West Design & Test Symposium, 2013

Extracting complete set of equations to analyze VHDL-AMS descriptions.
Proceedings of the East-West Design & Test Symposium, 2013

A probabilistic approach for counterexample generation to aid design debugging.
Proceedings of the East-West Design & Test Symposium, 2013

2012
Polynomial datapath synthesis and optimization based on vanishing polynomial over Z2m and algebraic techniques.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

BS 1149.1 extensions for an online interconnect fault detection and recovery.
Proceedings of the 2012 IEEE International Test Conference, 2012

Soft Error Analysis on Communication Channels in On-Chip Communication Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Effective RT-level software-based self-testing of embedded processor cores.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Power constraint testing for multi-clock domain SoCs using concurrent hybrid BIST.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

A Probabilistic and Constraint Based Approach for Low Power Test Generation.
Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011
Configurable architecture for memory BIST.
Proceedings of the 9th East-West Design & Test Symposium, 2011

Adaptation of Standard RT Level BIST Architectures for System Level Communication Testing.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Online Test Macro Scheduling and Assignment in MPSoC Design.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Mapping Transaction Level Faults to Stuck-At Faults in Communication Hardware.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Real-time embedded emotional controller.
Neural Computing and Applications, 2010

EDXY - A low cost congestion-aware routing algorithm for network-on-chips.
J. Syst. Archit., 2010

Using context based methods for test data compression.
Proceedings of the 2011 IEEE International Test Conference, 2010

A partitioning approach to improve reconfigurable neuron-inspired online BIST.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Near optimal machine learning based random test generation.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Low cost error tolerant motion estimation for H.264/AVC standard.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

A mixed HDL/PLI test package.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Virtual tester development using HDL/PLI.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Merit based directed random test generation (MDRTG) scheme for combinational circuits.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

ESL design methodology for architecture exploration.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Generating test patterns for sequential circuits using random patterns by PLI functions.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Architecture design and technical methodology for bus testing.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Assertion based verification in TLM.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

A TLM2.0 assertion library with centralized monitoring approach.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Facilitating testability of TLM FIFO: SystemC implementations.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

Code optimization for enhancing SystemC simulation time.
Proceedings of the 2010 East-West Design & Test Symposium, 2010

A reconfigurable online BIST for combinational hardware using digital neural networks.
Proceedings of the 15th European Test Symposium, 2010

Test Pattern Selection and Compaction for Sequential Circuits in an HDL Environment.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Sign Bit Reduction Encoding For Low Power Applications.
Signal Processing Systems, 2009

Emotion on FPGA: Model driven approach.
Expert Syst. Appl., 2009

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008
A Selective Trigger Scan Architecture for VLSI Testing.
IEEE Trans. Computers, 2008

Online Network-on-Chip Switch Fault Detection and Diagnosis Using Functional Switch Faults.
J. UCS, 2008

An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Stall Power Reduction in Pipelined Architecture Processors.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Enhanced TED: A New Data Structure for RTL Verification.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

"Plug & Test" at System Level via Testable TLM Primitives.
Proceedings of the 2008 IEEE International Test Conference, 2008

NoC Reconfiguration for Utilizing the Largest Fault-free Connected Sub-structure.
Proceedings of the 2008 IEEE International Test Conference, 2008

Reliability in Application Specific Mesh-Based NoC Architectures.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Functional testing approaches for "BIFST-able" tlm_fifo.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An IEEE 1500 compatible wrapper architecture for testing cores at transaction level.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

Automating Hardware/Software partitioning using dependency Graph.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

System level hardware design and simulation with SystemAda.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

An advanced method for synthesizing TLM2-based interfaces.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

Utilizing HDL simulation engines for accelerating design and test processes.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

Reliable NoC architecture utilizing a robust rerouting algorithm.
Proceedings of the 2008 East-West Design & Test Symposium, 2008

BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Low test application time resource binding for behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst., 2007

Low overhead DFT using CDFG by modifying controller.
IET Computers & Digital Techniques, 2007

Degradable mesh-based on-chip networks using programmable routing tables.
IEICE Electronic Express, 2007

A UML Based System Level Failure Rate Assessment Technique for SoC Designs.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

High Level Synthesis of Degradable ASICs Using Virtual Binding.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Programmable Routing Tables for Degradable Torus-Based Networks on Chips.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A New Approach for Design and Verification of Transaction Level Models.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

An Analytical Model for Reliability Evaluation of NoC Architectures.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

RT level reliability enhancement by constructing dynamic TMRS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A Configurable Transaction Level Model of a Generic Interconnection Part of Embedded Systems Used in an ESL Design Library.
Proceedings of the Forum on specification and Design Languages, 2007

APDL: A Processor Description Language For Design Space Exploration of Embedded Processors.
Proceedings of the Forum on specification and Design Languages, 2007

On-Chip Verification of NoCs Using Assertion Processors.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Mode.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A HW/SW Architecture to Reduce the Effects of Soft-Errors in Real-Time Operating System Services.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Using the inter- and intra-switch regularity in NoC switch testing.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Scan-Based Structure with Reduced Static and Dynamic Power Consumption.
J. Low Power Electronics, 2006

A Test Approach for Look-Up Table Based FPGAs.
J. Comput. Sci. Technol., 2006

ByZFAD: a low switching activity architecture for shift-and-add multipliers.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Ant colony based routing architecture for minimizing hot spots in NOCs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

An Optimized BIST Architecture for FPGA Look-Up Table Testing.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A New Protocol Stack Model for Network on Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Low-power and low-latency cluster topology for local traffic NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

DCim++: a C++ library for object oriented hardware design and distributed simulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A concurrent testing method for NoC switches.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

NoC Hot Spot minimization Using AntNet Dynamic Routing Algorithm.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Instruction-level test methodology for CPU core self-testing.
ACM Trans. Design Autom. Electr. Syst., 2005

An Effective VHDL-AMS Simulation Algorithm with Event Partitioning.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Flow Graph Technique for DFT Controller Modification.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low-power scan-path architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Combination of Assertion and HSAT Methods For Automated Test Vectors Generation.
Proceedings of the Forum on specification and Design Languages, 2005

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Simultaneous Reduction of Dynamic and Static Power in Scan Structures.
Proceedings of the 2005 Design, 2005

Enhancing Fault Simulation Performance by Dynamic Fault Clustering.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

ISC: Reconfigurable Scan-Cell Architecture for Low Power Testing.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

TED+: a data structure for microprocessor verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Digital design and implementation with field programmable devices.
Kluwer, ISBN: 978-1-4020-8011-1, 2005

2004
Using data compression in automatic test equipment for system-on-chip testing.
IEEE Trans. Instrumentation and Measurement, 2004

A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores.
J. Electronic Testing, 2004

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation.
J. Electronic Testing, 2004

Using Integer Equations to Check PSL Properties in RT Level Design.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Instruction level test methodology for CPU core software-based self-testing.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Property Checking based on Hierarchical Integer Equations.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003
Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Processor Testing Using an ADL Description and Genetic Algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003

A Low Power BIST Architecture for FPGA Look-Up Table Testing.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Dynamic Input Buffer Allocation (DIBA) for Fault Tolerant Ethernet Packet Switching.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Utilizing Various ADL Facets for Instruction Level CPU Test.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment.
Proceedings of the International Conference on Embedded Systems and Applications, 2003

The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Data Compression for System-on-Chip Testing Using ATE.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
An efficient BIST method for testing of embedded SRAMs.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Fault Simulation for VHDL Based Test Bench and BIST Evaluation.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
Hardware Description in Verilog.
Proceedings of the VLSI Handbook., 1999

1995
A Transistor Level Link for VHDL Simulation of VLSI Circuits.
Simulation, 1995

1993
Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
A high-level language for design and modeling of hardware.
J. Syst. Softw., 1992

1991
Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions.
Simulation, 1991

1984
Hardware Compilation from an RTL to a Storage Logic Array Target.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1984

1981
Structure Specification with a Procedural Hardware Description Language.
IEEE Trans. Computers, 1981

1979
Efficient simulation of AHPL.
Proceedings of the 16th Design Automation Conference, 1979


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