Paul E. Gronowski

According to our database1, Paul E. Gronowski authored at least 7 papers between 1995 and 2011.

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Bibliography

2011
A 32nm 3.1 billion transistor 12-wide-issue Itanium<sup>®</sup> processor for mission-critical servers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009
A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.
IEEE J. Solid State Circuits, 2009

2008
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

1998
High-performance microprocessor design.
IEEE J. Solid State Circuits, 1998

1996
A 433-MHz 64-b quad-issue RISC microprocessor.
IEEE J. Solid State Circuits, 1996

1995
A 300-MHz 64-b quad-issue CMOS RISC microprocessor.
IEEE J. Solid State Circuits, November, 1995

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU
Digit. Tech. J., 1995


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