Jayen Desai

According to our database, Jayen Desai authored at least 5 papers between 2006 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2016

The Xeon® Processor E5-2600 v3: a 22 nm 18-Core Product Family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Oscar Mendoza, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Brian Brock, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

IEEE J. Solid State Circuits, 2016

2015

4.5 The Xeon® processor E5-2600 v3: A 22nm 18-core product family.

William J. Bowhill, Blaine A. Stackhouse, Nevine Nassif, Zibing Yang, Arvind Raghavan, Charles Morganti, Chris Houghton, Dan Krueger, Olivier Franza, Jayen Desai, Jason Crop, Dave Bradley, Chris Bostak, Sal Bhimji, Matt Becker

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2009

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.

Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer

IEEE J. Solid State Circuits, 2009

2006

The implementation of a 2-core, multi-threaded itanium family processor.

Samuel Naffziger, Blaine A. Stackhouse, Tom Grutkowski, Doug Josephson, Jayen Desai, Elad Alon, Mark Horowitz

IEEE J. Solid State Circuits, 2006

A 90-nm variable frequency clock system for a power-managed itanium architecture processor.

Tim C. Fischer, Jayen Desai, Bruce Andrew Doyle, Samuel Naffziger, Ben Patella

IEEE J. Solid State Circuits, 2006