Paul G. A. Jespers

According to our database1, Paul G. A. Jespers authored at least 24 papers between 1962 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1982, "For leadership in microelectronics research, development, and education.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2015
Calculation of MOSFET distortion using the transconductance-to-current ratio (gm/ID).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2008
Modeling, Evaluation, and Comparison of CRZ and RSD Redundant Architectures for Two-Step A/D Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Sizing CMOS circuits by means of the gm/ID methodology and a compact model.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Comparison of redundant architectures for two-step ADCs.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Sizing low-voltage CMOS analog circuits.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
Analog circuit synthesis using standard EDA tools.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2003
Design of analog fuzzy logic controllers in CMOS technologies - implementation, test and application.
Kluwer, 2003

2002
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

2001
On Designing Mixed-Signal Fuzzy Logic Controllers as Embedded Subsystems in Standard CMOS Technologies.
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001

Embedded fuzzy control for automatic channel equalization after digital transmissions.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A 5.26 Mflips programmable analogue fuzzy logic controller in a standard CMOS 2.4 μ technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1997
Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology.
IEEE J. Solid State Circuits, 1997

1996
A g<sub>m</sub>/I<sub>D</sub> based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA.
IEEE J. Solid State Circuits, 1996

Design of SOI CMOS operational amplifiers for applications up to 300°C.
IEEE J. Solid State Circuits, 1996

1994
A 10-bit pipelined switched-current A/D converter.
IEEE J. Solid State Circuits, August, 1994

1993
Analog implementation of a Kohonen map with on-chip learning.
IEEE Trans. Neural Networks, 1993

1991
Analog VLSI Synapse Matrix with Enhanced Stochastic Computations.
Proceedings of the Artificial Neural Networks, 1991

1989
An analog VLSI implementation of Hopfield's neural network.
IEEE Micro, 1989

An Analog VLSI Architecture for Large Neural Networks.
Proceedings of the Neurocomputing - Algorithms, Architectures and Applications, Proceedings of the NATO Advanced Research Workshop on Neurocomputing Algorithms, Architectures and Applications, Les Arcs, France, February 27, 1989

A Single Chip 1024 Bits RSA Processor.
Proceedings of the Advances in Cryptology, 1989

1988
A large VLSI Hopfield network for pattern recognition problems.
Neural Networks, 1988

An algorithm for pattern recognition with VLSI neural networks.
Neural Networks, 1988

1980
Dedicated LSI for a Microprocessor-Controlled Hand-Carried OCR System.
IEEE Trans. Computers, 1980

1962
A new method to compute correlation functions (Abstr.).
IRE Trans. Inf. Theory, 1962


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