Boris Murmann
Orcid: 0000-0003-3417-8782Affiliations:
- Stanford University, USA
According to our database1,
Boris Murmann
authored at least 143 papers
between 2003 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to the design of digitally-assisted analog integrated circuits".
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on id.loc.gov
On csauthors.net:
Bibliography
2024
A 1024-Channel 268-nW/Pixel 36×36 μm<sup>2</sup>/Channel Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
IEEE J. Solid State Circuits, April, 2024
TinyForge: A Design Space Exploration to Advance Energy and Silicon Area Trade-offs in tinyML Compute Architectures with Custom Latch Arrays.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
2023
Data Compression Versus Signal Fidelity Tradeoff in Wired-OR Analog-to-Digital Compressive Arrays for Neural Recording.
IEEE Trans. Biomed. Circuits Syst., August, 2023
A 0.6-1.8-mW 3.4-dB NF Mixer-First Receiver With an N-Path Harmonic-Rejection Transformer-Mixer.
IEEE J. Solid State Circuits, 2023
Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables.
IEEE Access, 2023
A 1024-Channel 268 nW/pixel 36x36 μm<sup>2</sup>/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
High-Linearity High-Bandwidth (>20GHz) T&H Front Ends Using Active Bootstrapping and Heterogeneous SiGe/CMOS Circuit Co-Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
EMBER: A 100 MHz, 0.86 mm<sup>2</sup>, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference.
IEEE J. Solid State Circuits, 2022
IEEE Des. Test, 2022
Innovating at Speed and at Scale: A Next Generation Infrastructure for Accelerating Semiconductor Technologies.
CoRR, 2022
Improving the Energy Efficiency and Robustness of tinyML Computer Vision using Log-Gradient Input Images.
CoRR, 2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
A 56 GS/s 8-bit 0.011 mm<sup>2</sup> 4x Delta-Interleaved Switched-Capacitor DAC in 16nm FinFET CMOS.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Data Compression versus Signal Fidelity Trade-off in Wired-OR ADC Arrays for Neural Recording.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology.
IEEE Open J. Circuits Syst., 2021
A 2✖ Time-Interleaved 28-GS/s 8-Bit 0.03-mm<sup>2</sup> Switched-Capacitor DAC in 16-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2021
Stability of Gated Recurrent Unit Neural Networks: Convex Combination Formulation Approach.
J. Optim. Theory Appl., 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Going Beyond the Debye Length: Overcoming Charge Screening Limitations in Next-Generation Bioelectronic Sensors.
CoRR, 2020
IEEE Access, 2020
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Design Considerations for External Compensation Approaches to OLED Display Degradation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Separating the Effects of Batch Normalization on CNN Training Speed and Stability Using Classical Adaptive Filter Theory.
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2019
A Spectrum-Sensing DPD Feedback Receiver With 30× Reduction in ADC Acquisition Bandwidth and Sample Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Biomed. Circuits Syst., 2019
A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection.
IEEE J. Solid State Circuits, 2019
An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
Global Asymptotic Stability and Stabilization of Long Short-Term Memory Neural Networks with Constant Weights and Biases.
J. Optim. Theory Appl., 2019
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Long-Short Term Memory Neural Network Stability and Stabilization using Linear Matrix Inequalities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Memory-Optimal Direct Convolutions for Maximizing Classification Accuracy in Embedded Applications.
Proceedings of the 36th International Conference on Machine Learning, 2019
An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
Toward Always-On Mobile Object Detection: Energy Versus Performance Tradeoffs for Embedded HOG Feature Extraction.
IEEE Trans. Circuits Syst. Video Technol., 2018
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018
A 56 Gb/s 6 mW 300 um<sup>2</sup> inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI.
IEEE J. Solid State Circuits, 2017
A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection.
IEEE J. Solid State Circuits, 2017
Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
2016
The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.
IEEE Commun. Mag., 2016
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
Data converter reflections: 19 papers from the last ten years that deserve a second look.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Calculation of MOSFET distortion using the transconductance-to-current ratio (gm/ID).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
A 0.6 V-2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Static Integral Nonlinearity Modeling and Calibration of Measured and Synthetic Pipeline Analog-to-Digital Converters.
IEEE Trans. Instrum. Meas., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
IEEE Trans. Instrum. Meas., 2013
Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A ΔΣ Interface for MEMS Accelerometers Using Electrostatic Spring Constant Modulation for Cancellation of Bondwire Capacitance Drift.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2012
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration.
IEEE J. Solid State Circuits, 2011
Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using <i>g<sub>m</sub></i>/<i>I<sub>D</sub></i> Lookup Table Methodology.
IEICE Trans. Electron., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the 37th European Solid-State Circuits Conference, 2011
2010
The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass.
IEEE J. Solid State Circuits, 2010
A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters.
IEEE J. Sel. Top. Signal Process., 2009
A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
A/D converter trends: Power dissipation, scaling and digitally assisted architectures.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs.
IEEE Trans. Instrum. Meas., 2007
IEEE J. Solid State Circuits, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
A background correction technique for timing errors in time-interleaved analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
2003
IEEE J. Solid State Circuits, 2003