Boris Murmann

According to our database1, Boris Murmann authored at least 108 papers between 2004 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2015, "For contributions to the design of digitally-assisted analog integrated circuits".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2020
Distortion Analysis of RC Integrators With Wideband Input Signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Low-Rank Training of Deep Neural Networks for Emerging Memory Technology.
CoRR, 2020

Going Beyond the Debye Length: Overcoming Charge Screening Limitations in Next-Generation Bioelectronic Sensors.
CoRR, 2020

Separating the Effects of Batch Normalization on CNN Training Speed and Stability Using Classical Adaptive Filter Theory.
CoRR, 2020

Analog IC Design Using Precomputed Lookup Tables: Challenges and Solutions.
IEEE Access, 2020

A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A Spectrum-Sensing DPD Feedback Receiver With 30× Reduction in ADC Acquisition Bandwidth and Sample Rate.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Data-Compressive Wired-OR Readout for Massively Parallel Neural Recording.
IEEE Trans. Biomed. Circuits Syst., 2019

A Data-Compressive 1.5/2.75-bit Log-Gradient QVGA Image Sensor With Multi-Scale Readout for Always-On Object Detection.
IEEE J. Solid State Circuits, 2019

An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019

Global Asymptotic Stability and Stabilization of Long Short-Term Memory Neural Networks with Constant Weights and Biases.
J. Optim. Theory Appl., 2019

Custom Sub-Systems and Circuits for Deep Learning: Guest Editorial Overview.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

A Data-Compressive 1.5b/2.75b Log-Gradient QVGA Image Sensor with Multi-Scale Readout for Always-On Object Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Sound Classification using Summary Statistics and N-Path Filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Long-Short Term Memory Neural Network Stability and Stabilization using Linear Matrix Inequalities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Memory-Optimal Direct Convolutions for Maximizing Classification Accuracy in Embedded Applications.
Proceedings of the 36th International Conference on Machine Learning, 2019

An Energy Harvester Using Image Sensor Pixels With Cold Start and Over 96% MPPT Efficiency.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

RRAM-Based In-Memory Computing for Embedded Deep Neural Networks.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018
Toward Always-On Mobile Object Detection: Energy Versus Performance Tradeoffs for Embedded HOG Feature Extraction.
IEEE Trans. Circuits Syst. Video Technol., 2018

An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

An always-on 3.8μJ/86% CIFAR-10 mixed-signal binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Some Local Stability Properties of an Autonomous Long Short-Term Memory Neural Network Model.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A New Figure of Merit Equation for Analog-to-Digital Converters in CMOS Image Sensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Clock Synchronous Reset and Skew Calibration of 65GS/s ADCs in A Multi-Lane Coherent Receiver.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs.
Proceedings of the 55th Annual Design Automation Conference, 2018

A 56 Gb/s 6 mW 300 um<sup>2</sup> inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 14-Bit 30-MS/s 38-mW SAR ADC Using Noise Filter Gear Shifting.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

Metastablility in SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Pixel Pitch-Matched Ultrasound Receiver for 3-D Photoacoustic Imaging With Integrated Delta-Sigma Beamformer in 28-nm UTBB FD-SOI.
IEEE J. Solid State Circuits, 2017

A Mixer Front End for a Four-Channel Modulated Wideband Converter With 62-dB Blocker Rejection.
IEEE J. Solid State Circuits, 2017

Approximate SRAM for Energy-Efficient, Privacy-Preserving Convolutional Neural Networks.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Foreword: Intelligent Chips for a Smart World.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Session 1 overview: Plenary Session.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

SRAM voltage scaling for energy-efficient convolutional neural networks.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

LogNet: Energy-efficient neural networks using logarithmic computation.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
Convolutional Neural Networks using Logarithmic Data Representation.
CoRR, 2016

The successive approximation register ADC: a versatile building block for ultra-low- power to ultra-high-speed applications.
IEEE Commun. Mag., 2016

A 0.003 mm<sup>2</sup> 5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

Data converter reflections: 19 papers from the last ten years that deserve a second look.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortion.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Closed-Loop Reconfigurable Switched-Capacitor DC-DC Converter for Sub-mW Energy Harvesting Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015

15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Calculation of MOSFET distortion using the transconductance-to-current ratio (gm/ID).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Mixer-based subarray beamforming for sub-Nyquist sampling ultrasound architectures.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

A 0.6 V-2.4 V input, fully integrated reconfigurable switched-capacitor DC-DC converter for energy harvesting sensor tags.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Mixed-signal circuits for embedded machine-learning applications.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Static Integral Nonlinearity Modeling and Calibration of Measured and Synthetic Pipeline Analog-to-Digital Converters.
IEEE Trans. Instrum. Meas., 2014

Mismatch Characterization of Small Metal Fringe Capacitors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A Four-Channel, ±36 V, 780 kHz Piezo Driver Chip for Structural Health Monitoring.
IEEE J. Solid State Circuits, 2014

Teaching an old dog new tricks: Views on the future of mixed-signal IC design.
Proceedings of the 2014 International Test Conference, 2014

Design and optimization of continuous-time filters using geometric programming.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Low-rate identification of memory polynomials.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Low-voltage organic transistors for flexible electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

A 160 MS/s, 11.1 mW, single-channel pipelined SAR ADC with 68.3 dB SNDR.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Dynamic Calibration of Undersampled Pipelined ADCs by Frequency Domain Filtering.
IEEE Trans. Instrum. Meas., 2013

Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A ΔΣ Interface for MEMS Accelerometers Using Electrostatic Spring Constant Modulation for Cancellation of Bondwire Capacitance Drift.
IEEE J. Solid State Circuits, 2013

A 256 Pixel Magnetoresistive Biosensor Microarray in 0.18 µm CMOS.
IEEE J. Solid State Circuits, 2013

F6: Mixed-signal/RF design and modeling in next-generation CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Session 26 overview: High-speed data converters.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A/D converter circuit and architecture design for high-speed data communication.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A 12-b, 30-MS/s, 2.95-mW Pipelined ADC Using Single-Stage Class-AB Amplifiers and Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2012

HermesE: A 96-Channel Full Data Rate Direct Neural Interface in 0.13 µm CMOS.
IEEE J. Solid State Circuits, 2012

Low-power analog signal processing.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Towards an integrated circuit design of a compressed sampling wireless receiver.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

A -131-dBc/Hz, 20-MHz MEMS oscillator with a 6.9-mW, 69-kΩ, gain-tunable CMOS TIA.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Feedforward Interference Cancellation Architecture for Short-Range Wireless Communication.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration.
IEEE J. Solid State Circuits, 2011

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using <i>g<sub>m</sub></i>/<i>I<sub>D</sub></i> Lookup Table Methodology.
IEICE Trans. Electron., 2011

Data converter breakthroughs in retrospect.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass.
IEEE J. Solid State Circuits, 2010

Trends in Low-Power, Digitally Assisted A/D Conversion.
IEICE Trans. Electron., 2010

A 3V 6b successive-approximation ADC using complementary organic thin-film transistors on glass.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Portable biomarker detection with magnetic nanotags.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of analog circuits using organic field-effect transistors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A 12-bit, 30-MS/s, 2.95-mW pipelined ADC using single-stage class-AB amplifiers and deterministic background calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters.
IEEE J. Sel. Top. Signal Process., 2009

A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification.
IEEE J. Solid State Circuits, 2009

A 56MΩ CMOS TIA for MEMS applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Calculation of Total Integrated Noise in Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Unusual Data-Converter Techniques.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Characterizing the Impact of Substrate Noise on High-Speed Flash ADCs.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Hybrid Integration of Bandgap Reference Circuits Using Silicon ICs and Germanium Devices.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Digitally enhanced analog circuits: System aspects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Predictive control algorithm for phase-locked loops.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Digital correction of dynamic track-and-hold errors providing SFDR ≫ 83 dB up to fin = 470 MHz.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

A/D converter trends: Power dissipation, scaling and digitally assisted architectures.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs.
IEEE Trans. Instrum. Meas., 2007

A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling.
IEEE J. Solid State Circuits, 2007

A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Low-Power, 6-bit Time-Interleaved SAR ADC Using OFDM Pilot Tone Calibration.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
System embedded ADC calibration for OFDM receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Digitally Assisted Analog Circuits.
IEEE Micro, 2006

4.25 Gb/s laser driver: design challenges and EDA tool limitations.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A background correction technique for timing errors in time-interleaved analog-to-digital converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A low-power distributed wide-band LNA in 0.18µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Digitally Assisted Analog Integrated Circuits.
ACM Queue, 2004


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