Paul Theo Gonciari

According to our database1, Paul Theo Gonciari authored at least 8 papers between 2002 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2005
Synchronization overhead in SOC compressed test.
IEEE Trans. Very Large Scale Integr. Syst., 2005

2004
A compression-driven test access mechanism design approach.
Proceedings of the 9th European Test Symposium, 2004

2003
Addressing useless test data in core-based system-on-a-chip test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Variable-length input Huffman coding for system-on-a-chip test.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Test Data Compression: The System Integrator's Perspective.
Proceedings of the 2003 Design, 2003

2002
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.
Proceedings of the 2002 Design, 2002


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