Bashir M. Al-Hashimi

According to our database1, Bashir M. Al-Hashimi authored at least 252 papers between 1998 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2009, "For contributions to low power integrated circuits and systems".

Timeline

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Bibliography

2019
Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores.
IEEE Trans. VLSI Syst., 2019

Momentum: Power-neutral Performance Scaling with Intrinsic MPPT for Energy Harvesting Computing Systems.
ACM Trans. Embedded Comput. Syst., 2019

Low-Complexity Architecture for Cyber-Physical Systems Model Identification.
IEEE Trans. on Circuits and Systems, 2019

Arbitrarily Parallel Turbo Decoding for Ultra-Reliable Low Latency Communication in 3GPP LTE.
IEEE Journal on Selected Areas in Communications, 2019

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations.
IEEE Communications Surveys and Tutorials, 2019

BRB: Mitigating Branch Predictor Side-Channels.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018
Inter-Cluster Thread-to-Core Mapping and DVFS on Heterogeneous Multi-Cores.
IEEE Trans. Multi-Scale Computing Systems, 2018

Runtime Performance and Power Optimization of Parallel Disparity Estimation on Many-Core Platforms.
ACM Trans. Embedded Comput. Syst., 2018

High-Speed Low-Complexity Guided Image Filtering-Based Disparity Estimation.
IEEE Trans. on Circuits and Systems, 2018

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations.
IEEE Trans. on Circuits and Systems, 2018

Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A model-based framework for software portability and verification in embedded power management systems.
Journal of Systems Architecture - Embedded Systems Design, 2018

An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems.
Proceedings of the 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems, 2018

Hardware-Validated CPU Performance and Energy Modelling.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Collective-Aware System-on-Chips for Dependable IoT Applications.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Workload-Aware Runtime Energy Management for HPC Systems.
Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Graceful Performance Adaption through Hardware-Software Interaction for Autonomous Battery Management of Multicore Smartphones.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018

Online concurrent workload classification for multi-core energy management.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure.
IEEE Trans. VLSI Syst., 2017

Nucleus: Finding the Sharing Limit of Heterogeneous Cores.
ACM Trans. Embedded Comput. Syst., 2017

Energy-Efficient Run-Time Mapping and Thread Partitioning of Concurrent OpenCL Applications on CPU-GPU MPSoCs.
ACM Trans. Embedded Comput. Syst., 2017

Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems.
IEEE Trans. on Circuits and Systems, 2017

Aging Benefits in Nanometer CMOS Designs.
IEEE Trans. on Circuits and Systems, 2017

Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Learning-Based Run-Time Power and Energy Management of Multi/Many-Core Systems: Current and Future Trends.
J. Low Power Electronics, 2017

Flexible iterative receiver architecture for wireless sensor networks: a joint source and channel coding design example.
IET Wireless Sensor Systems, 2017

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder.
IEEE Access, 2017

A High-Throughput FPGA Architecture for Joint Source and Channel Decoding.
IEEE Access, 2017

A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Empirical CPU power modelling and estimation in the gem5 simulator.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Exploring ARM mbed support for transient computing in energy harvesting IoT systems.
Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Online tuning of Dynamic Power Management for efficient execution of interactive workloads.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Reliable mapping and partitioning of performance-constrained openCL applications on CPU-GPU MPSoCs.
Proceedings of the 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, 2017

Hardware and software innovations in energy-efficient system-reliability monitoring.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Energy-driven computing: Rethinking the design of energy harvesting systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Machine learning for run-time energy optimisation in many-core systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Reliable Power Gating With NBTI Aging Benefits.
IEEE Trans. VLSI Syst., 2016

Sequence-Aware Watermark Design for Soft IP Embedded Processors.
IEEE Trans. VLSI Syst., 2016

Two-Phase Low-Energy N-Modular Redundancy for Hard Real-Time Multi-Core Systems.
IEEE Trans. Parallel Distrib. Syst., 2016

Adaptive and Hierarchical Runtime Manager for Energy-Aware Thermal Management of Embedded Systems.
ACM Trans. Embedded Comput. Syst., 2016

Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Hibernus++: A Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Graceful Performance Modulation for Power-Neutral Transient Computing Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Workload Change Point Detection for Runtime Thermal Management of Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Survey of FPGA-Based LDPC Decoders.
IEEE Communications Surveys and Tutorials, 2016

20 Years of Turbo Coding and Energy-Aware Design Guidelines for Energy-Constrained Wireless Applications.
IEEE Communications Surveys and Tutorials, 2016

Improving the Tolerance of Stochastic LDPC Decoders to Overclocking-Induced Timing Errors: A Tutorial and a Design Example.
IEEE Access, 2016

Stochastic Computing Improves the Timing-Error Tolerance and Latency of Turbo Decoders: Design Guidelines and Tradeoffs.
IEEE Access, 2016

VLSI Implementation of Fully Parallel LTE Turbo Decoders.
IEEE Access, 2016

Implementation of a Fully-Parallel Turbo Decoder on a General-Purpose Graphics Processing Unit.
IEEE Access, 2016

1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications.
IEEE Access, 2016

Exponential Golomb and Rice Error Correction Codes for Generalized Near-Capacity Joint Source and Channel Coding.
IEEE Access, 2016

A Scalable Turbo Decoding Algorithm for High-Throughput Network-on-Chip Implementation.
IEEE Access, 2016

Co-optimization of fault tolerance, wirelength and temperature mitigation in TSV-based 3D ICs.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Thermally-aware composite run-time CPU power models.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

BTI aware thermal management for reliable DVFS designs.
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

The slowdown or race-to-idle question: Workload-aware energy optimization of SMT multicore platforms under process variation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Online Fault Tolerance Technique for TSV-Based 3-D-IC.
IEEE Trans. VLSI Syst., 2015

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Hibernus: Sustaining Computation During Intermittent Supply for Energy-Harvesting Systems.
Embedded Systems Letters, 2015

Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design.
Proceedings of the 3rd International Workshop on Energy Harvesting & Energy Neutral Sensing Systems, 2015

Approaches to Transient Computing for Energy Harvesting Systems: A Quantitative Evaluation.
Proceedings of the 3rd International Workshop on Energy Harvesting & Energy Neutral Sensing Systems, 2015

Application-specific memory protection policies for energy-efficient reliable design.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Towards Automatic Code Generation of Run-Time Power Management for Embedded Systems Using Formal Methods.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Hardware-software interaction for run-time power optimization: A case study of embedded Linux on multicore smartphones.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

BTI and leakage aware dynamic voltage scaling for reliable low power cache memories.
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Adaptive iterative detection for expediting the convergence of a serially concatenated Unary Error Correction decoder, turbo decoder and an iterative demodulator.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems.
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

Diagnosis of power switches with power-distribution-network consideration.
Proceedings of the 20th IEEE European Test Symposium, 2015

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating.
Proceedings of the 20th IEEE European Test Symposium, 2015

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Active Mode Subclock Power Gating.
IEEE Trans. VLSI Syst., 2014

Delay Test for Diagnosis of Power Switches.
IEEE Trans. VLSI Syst., 2014

Efficient Variation-Aware Delay Fault Simulation Methodology for Resistive Open and Bridge Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Learner-battery interaction in energy-aware learning multimedia systems.
Proceedings of the 13th International Conference on Mobile and Ubiquitous Multimedia, 2014

Energy-Aware Streaming Multimedia Adaptation: An Educational Perspective.
Proceedings of the 12th International Conference on Advances in Mobile Computing and Multimedia, 2014

Clock-modulation based watermark for protection of embedded processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Advanced SIMD: Extending the reach of contemporary SIMD architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

High Quality Testing of Grid Style Power Gating.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Energy-Conscious Turbo Decoder Design: A Joint Signal Processing and Transmit Energy Reduction Approach.
IEEE Trans. Vehicular Technology, 2013

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks.
IEEE Trans. VLSI Syst., 2013

Improved State Integrity of Flip-Flops for Voltage Scaled Retention Under PVT Variation.
IEEE Trans. on Circuits and Systems, 2013

Analysis of voltage- and clock-scaling-induced timing errors in stochastic LDPC decoders.
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013

Tunable vibration energy harvester.
Proceedings of the 1st International Workshop on Energy Neutral Sensing Systems, 2013

Applying of Quality of Experience to system optimisation.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Hardware reliability of embedded systems: Are we there yet?
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Content-Aware Power Saving Multimedia Adaptation for Mobile Learning.
Proceedings of the Seventh International Conference on Next Generation Mobile Apps, 2013

Energy-Aware Adaptation of Educational Multimedia in Mobile Learning.
Proceedings of the 11th International Conference on Advances in Mobile Computing & Multimedia, 2013

Impact of PVT variation on delay test of resistive open and resistive bridge defects.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A survey of multi-source energy harvesting systems.
Proceedings of the Design, Automation and Test in Europe, 2013

DoE-based performance optimization of energy management in sensor nodes powered by tunable energy-harvesters.
Proceedings of the Design, Automation and Test in Europe, 2013

MALEC: a multiple access low energy cache.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Photovoltaic Sample-and-Hold Circuit Enabling MPPT Indoors for Low-Power Systems.
IEEE Trans. on Circuits and Systems, 2012

An Explicit Linearized State-Space Technique for Accelerated Simulation of Electromagnetic Vibration Energy Harvesters.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Low-Energy Standby-Sparing for Hard Real-Time Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

System-level design optimization of reliable and low power multiprocessor system-on-chip.
Microelectronics Reliability, 2012

dRail: A Novel Physical Layout Methodology for Power Gated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

Enabling the discovery of Adaptive Learning Resources for Mobile Learner.
Proceedings of the 11th International Conference on Mobile and Contextual Learning, 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Accelerators and emulators: Can they become the platform of choice for hardware verification?
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Coordinate Rotation Based Low Complexity N-D FastICA Algorithm and Architecture.
IEEE Trans. Signal Processing, 2011

Algorithm and Architecture for N-D Vector Cross-Product Computation.
IEEE Trans. Signal Processing, 2011

Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes.
IEEE Trans. on Circuits and Systems, 2011

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

A low-power, distributed, pervasive healthcare system for supporting memory.
Proceedings of the First ACM MobiHoc Workshop on Pervasive Wireless Healthcare, 2011

Investigation into voltage and process variation-aware manufacturing test.
Proceedings of the 2011 IEEE International Test Conference, 2011

Simplified logic design methodology for fuzzy membership function based robust detection of maternal modulus maxima location: A low complexity Fetal ECG extraction architecture for mobile health monitoring systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Improved DFT for Testing Power Switches.
Proceedings of the 16th European Test Symposium, 2011

Ultra low-power photovoltaic MPPT technique for indoor and outdoor wireless sensor nodes.
Proceedings of the Design, Automation and Test in Europe, 2011

Accelerated simulation of tunable vibration energy harvesting systems using a linearised state-space technique.
Proceedings of the Design, Automation and Test in Europe, 2011

Sub-clock power-gating technique for minimising leakage power during active mode.
Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks.
IEEE Trans. VLSI Syst., 2010

An Energy-Efficient Error Correction Scheme for IEEE 802.15.4 Wireless Sensor Networks.
IEEE Trans. on Circuits and Systems, 2010

Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Fault-tolerance techniques for hybrid CMOS/nanoarchitecture.
IET Computers & Digital Techniques, 2010

Design of Fixed-Point Processing Based Turbo Codes Using Extrinsic Information Transfer Charts.
Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010

Modeling the impact of process variation on resistive bridge defects.
Proceedings of the 2011 IEEE International Test Conference, 2010

Scan based methodology for reliable state retention power gating designs.
Proceedings of the Design, Automation and Test in Europe, 2010

Soft error-aware design optimization of low power and time-constrained embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Evaluation and design exploration of solar harvested-energy prediction algorithm.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Memory Reduction Methodology for Distributed-Arithmetic-Based DWT/IDWT Exploiting Data Symmetry.
IEEE Trans. on Circuits and Systems, 2009

Diagnosis of Multiple-Voltage Design With Bridge Defect.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Process Variation-Aware Test for Resistive Bridges.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip.
J. Low Power Electronics, 2009

Defect-tolerant n2-transistor structure for reliable nanoelectronic designs.
IET Computers & Digital Techniques, 2009

Hardware reduction methodology for 2-dimensional kurtotic fastica based on algorithmic analysis and architectural symmetry.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Energy-Aware Simulation for Wireless Sensor Networks.
Proceedings of the Sixth Annual IEEE Communications Society Conference on Sensor, 2009

Design of a low power MPEG-1 motion vector reconstructor.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Defect tolerance in hybrid nano/CMOS architecture using tagging mechanism.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

HSPICE implementation of a numerically efficient model of CNT transistor.
Proceedings of the Forum on specification and Design Languages, 2009

An automated design flow for vibration-based energy harvester systems.
Proceedings of the Design, Automation and Test in Europe, 2009

Variation resilient adaptive controller for subthreshold circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.
Proceedings of the Design, Automation and Test in Europe, 2009

Selective state retention design using symbolic simulation.
Proceedings of the Design, Automation and Test in Europe, 2009

A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Bridging Fault Test Method With Adaptive Power Management Awareness.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Subthreshold FIR Filter Architecture for Ultra Low Power Applications.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Reduced Z-datapath Cordic Rotator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A New Approach for Transient Fault Injection Using Symbolic Simulation.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

An Empirical Energy Model for Supercapacitor Powered Wireless Sensor Nodes.
Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

A Structured Hardware/Software Architecture for Embedded Sensor Nodes.
Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

Iterative Decoding for Redistributing Energy Consumption in Wireless Sensor Networks.
Proceedings of the 17th International Conference on Computer Communications and Networks, 2008

VHDL-AMS Implementation of a Numerical Ballistic CNT Model.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation.
Proceedings of the Forum on specification and Design Languages, 2008

Advancement in color image processing using Geometric Algebra.
Proceedings of the 2008 16th European Signal Processing Conference, 2008

Bridge Defect Diagnosis for Multiple-Voltage Design.
Proceedings of the 13th European Test Symposium, 2008

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Integrated approach to energy harvester mixed technology modelling and performance optimisation.
Proceedings of the Design, Automation and Test in Europe, 2008

Serialized Asynchronous Links for NoC.
Proceedings of the Design, Automation and Test in Europe, 2008

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density.
Proceedings of the Design, Automation and Test in Europe, 2008

Asynchronous transient resilient links for NoC.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

The Superchip: Innovative teaching of IC design and manufacture.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Hardware Dependability in the Presence of Soft Errors.
Proceedings of the Visions of Computer Science, 2008

Variation Aware Analysis of Bridging Fault Testing.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Hardware development for pervasive healthcare systems: Current status and future directions.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Transistor-level based defect tolerance for reliable nanoelectronics.
Proceedings of the 6th ACS/IEEE International Conference on Computer Systems and Applications, 2008

2007
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.
IEEE Trans. VLSI Syst., 2007

Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
ACM Trans. Design Autom. Electr. Syst., 2007

Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A fast, numerical circuit-level model of carbon nanotube transistor.
Proceedings of the 2007 IEEE International Symposium on Nanoscale Architectures, 2007

Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Architecture Level Power-Performance Tradeoffs for Pipelined Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Testing of Level Shifters in Multiple Voltage Designs.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
IEEE Trans. VLSI Syst., 2006

Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.
ACM Trans. Embedded Comput. Syst., 2006

Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Reducing Power Dissipation in SRAM during Test.
J. Low Power Electronics, 2006

New JETTA Editors, 2006.
J. Electronic Testing, 2006

Conference Reports.
IEEE Design & Test of Computers, 2006

Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Enhancing Delay Fault Coverage through Low Power Segmented Scan.
Proceedings of the 11th European Test Symposium, 2006

On-Chip Time Measurement Architecture with Femtosecond Timing Resolution.
Proceedings of the 11th European Test Symposium, 2006

Dynamic Voltage Scaling Aware Delay Fault Testing.
Proceedings of the 11th European Test Symposium, 2006

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Minimizing test power in SRAM through reduction of pre-charge activity.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Improving routing efficiency for network-on-chip through contention-aware input selection.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Cache size selection for performance, energy and reliability of time-constrained systems.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Synchronization overhead in SOC compressed test.
IEEE Trans. VLSI Syst., 2005

Application of analog adaptive filters for dynamic sensor compensation.
IEEE Trans. Instrumentation and Measurement, 2005

Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A novel switched-current phase locked loop.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Battery-aware dynamic voltage scaling in multiprocessor embedded system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A programmable time measurement architecture for embedded memory characterization.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Rapid Generation of Thermal-Safe Test Schedules.
Proceedings of the 2005 Design, 2005

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.
Proceedings of the 2005 Design, 2005

2004
Iterative schedule optimization for voltage scalable distributed embedded systems.
ACM Trans. Embedded Comput. Syst., 2004

New high-order filter structures using only single-ended-input OTAs and grounded capacitors.
IEEE Trans. on Circuits and Systems, 2004

Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Testability Trade-Offs for BIST Data Paths.
J. Electronic Testing, 2004

Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.
Proceedings of the Integrated Circuit and System Design, 2004

Analogue adaptive filters using wave synthesis technique.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Power-conscious design methodology for class-A switched-current wave filters.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A compression-driven test access mechanism design approach.
Proceedings of the 9th European Test Symposium, 2004

Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.
Proceedings of the 2004 Design, 2004

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.
Proceedings of the 2004 Design, 2004

System-level design techniques for energy-efficient embedded systems.
Springer, ISBN: 978-1-4020-7750-0, 2004

2003
Addressing useless test data in core-based system-on-a-chip test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Variable-length input Huffman coding for system-on-a-chip test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Power-Conscious Test Synthesis and Scheduling.
IEEE Design & Test of Computers, 2003

Load cell response correction using analog adaptive techniques.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A CAD methodology for switched current analog IP cores.
Proceedings of 9th IEEE International Conference on Emerging Technologies and Factory Automation, 2003

Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
Proceedings of the 2003 Design, 2003

A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities.
Proceedings of the 2003 Design, 2003

Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.
Proceedings of the 2003 Design, 2003

Test Data Compression: The System Integrator's Perspective.
Proceedings of the 2003 Design, 2003

2002
Power profile manipulation: a new approach for reducing test application time under power constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.
IEEE Trans. Computers, 2002

Synthesizing Energy-Efficient Embedded Systems with LOPOCOS.
Design Autom. for Emb. Sys., 2002

Guest Editor Introduction.
Design Autom. for Emb. Sys., 2002

Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Application of group delay equalisation in testing fully-balanced OTA-C filters.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Scan Architecture for Shift and Capture Cycle Power Reduction.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems.
Proceedings of the 2002 Design, 2002

Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.
Proceedings of the 2002 Design, 2002

Symbolic model checking of Dual Transition Petri Nets.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Considering power variations of DVS processing elements for energy minimisation in distributed systems.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Power constrained test scheduling using power profile manipulation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Dual transitions petri net based modelling technique for embedded systems specification.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Testability trade-offs for BIST RTL data paths: the case for three dimensional design space.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
BIST hardware synthesis for RTL data paths based on testcompatibility classes.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Power conscious test synthesis and scheduling for BIST RTL data paths.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.
Proceedings of the 2000 Design, 2000

1999
New differential coefficient coding algorithm for recursive FIR filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.
Proceedings of the 1999 Design, 1999

1998
Correction to the Proof of Theorem 2 in "Parallel Signature Analysis Design with Bounds on Aliasing".
IEEE Trans. Computers, 1998


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