Pawan Sehgal

According to our database, Pawan Sehgal authored at least 4 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 14-bit 6.7 MS/s 0.018 mm² 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications.

Sanjoy Kumar Dey, Arun Kumar Barman, Pawan Sehgal, Mukul Sarkar, Shouribrata Chatterjee

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

2016

An effective and efficient algorithm to analyse and debug clock propagation issues.

Pawan Sehgal, Aditi Sharma, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair.

Pawan Sehgal, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques.

Nidhi Batra, Pawan Sehgal, Shashwat Kaushik, Mohammad S. Hashmi, Sudesh Bhalla, Anuj Grover

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016