Peer Johannsen

According to our database, Peer Johannsen authored at least 5 papers between 2001 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2002

Speeding up hardware verification by automated data path scaling.

Peer Johannsen

PhD thesis, 2002

2001

Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.

Peer Johannsen, Rolf Drechsler

Proceedings of the SOC Design Methodologies, 2001

Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking.

Peer Johannsen

Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction.

Peer Johannsen

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

Utilizing High-Level Information for Formal Hardware Verification.

Peer Johannsen, Rolf Drechsler

Proceedings of the Advanced Computer Systems, Eighth International Conference, 2001