Rolf Drechsler

According to our database1, Rolf Drechsler authored at least 651 papers between 1992 and 2019.

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Awards

IEEE Fellow

IEEE Fellow 2015, "For contributions to test and verification of electronic circuits and systems".

Timeline

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Bibliography

2019
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits.
IEEE Trans. VLSI Syst., 2019

Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. VLSI Syst., 2019

Security validation of VP-based SoCs using dynamic information flow tracking.
it - Information Technology, 2019

Evaluation of (power) side-channels in cryptographic implementations.
it - Information Technology, 2019

Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits.
Proceedings of the 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, 2019

Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements.
Proceedings of the IEEE Latin American Test Symposium, 2019

Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Look what I can do: acquisition of programming skills in the context of living labs.
Proceedings of the 41st International Conference on Software Engineering: Software Engineering Education and Training, 2019

Automated Analysis of Virtual Prototypes at Electronic System Level.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Accuracy and Compactness in Decision Diagrams for Quantum Computation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Better Late Than Never : Verification of Embedded Systems After Deployment.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Verifying Instruction Set Simulators using Coverage-guided Fuzzing*.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Data Flow Testing for SystemC-AMS Timed Data Flow Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Temporal Tracing of On-Chip Signals using Timeprints.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable design for field-coupled nanocomputing circuits.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Maximizing power state cross coverage in firmware-based power management.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners.
Proceedings of the 18th ACM International Conference on Interaction Design and Children, 2019

2018
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Logic Synthesis for RRAM-Based In-Memory Computing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

On the complexity of design tasks for Digital Microfluidic Biochips.
Microelectronics Journal, 2018

Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams.
Microelectronics Journal, 2018

Behaviour Driven Development for Hardware Design.
IPSJ Trans. System LSI Design Methodology, 2018

The complexity of error metrics.
Inf. Process. Lett., 2018

Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements.
Computer Languages, Systems & Structures, 2018

Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

Multi-objective Synthesis of Quantum Circuits Using Genetic Programming.
Proceedings of the Reversible Computation - 10th International Conference, 2018

Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

Generation and Validation of Frame Conditions in Formal Models.
Proceedings of the Model-Driven Engineering and Software Development, 2018

Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence.
Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems.
Proceedings of the Dynamics in Logistics, 2018

Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Keynotes: Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

Logic Synthesis for In-memory Computing Using Resistive Memories.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Logic Design Using Memristors: An Emerging Technology.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Synthesis of Reversible Circuits Using Conventional Hardware Description Languages.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

IC/IP piracy assessment of reversible logic.
Proceedings of the International Conference on Computer-Aided Design, 2018

PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers.
Proceedings of the International Conference on Computer-Aided Design, 2018

SAT-Lancer: A Hardware SAT-Solver for Self-Verification.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Automatic Design of Microfluidic Devices.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Extensible and Configurable RISC-V Based Virtual Prototype.
Proceedings of the 2018 Forum on Specification & Design Languages, 2018

Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Towards Reversed Approximate Hardware Design.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Natural Language Based Power Domain Partitioning.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018

An exact method for design exploration of quantum-dot cellular automata.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improved synthesis of Clifford+T quantum functionality.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Resilience evaluation via symbolic fault injection on intermediate code.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards fully automated TLM-to-RTL property refinement.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Testbench qualification for SystemC-AMS timed data flow models.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Approximate hardware generation using symbolic computer algebra employing grobner basis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Approximation-aware testing for approximate circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

metaSMT: focus on your application and not on solver integration.
STTT, 2017

An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs.
J. Low Power Electronics, 2017

Synthesis of optical circuits using binary decision diagrams.
Integration, 2017

A PLiM Computer for the Internet of Things.
IEEE Computer, 2017

Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements.
Proceedings of the 2017 IEEE Symposium Series on Computational Intelligence, 2017

Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report.
Proceedings of the Reversible Computation - 9th International Conference, 2017

More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Yise - a novel framework for boolean networks using y-inverter graphs.
Proceedings of the 15th ACM-IEEE International Conference on Formal Methods and Models for System Design, 2017

Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Error Bounded Exact BDD Minimization in Approximate Computing.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

OR-Inverter Graphs for the Synthesis of Optical Circuits.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Extensions to the Reversible Hardware Description Language SyReC.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Towards lightweight satisfiability solvers for self-verification.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Early SoC security validation by VP-based static information flow analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

ProACt: A Processor for High Performance On-demand Approximate Computing.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization.
Proceedings of the Genetic and Evolutionary Computation Conference, 2017

Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction.
Proceedings of the Formal Modeling and Analysis of Timed Systems, 2017

Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach.
Proceedings of the Languages, Design Methods, and Tools for Electronic System Design, 2017

Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach.
Proceedings of the 2017 Forum on Specification and Design Languages, 2017

Foreword.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Unintrusive aging analysis based on offline learning.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Reconfigurable TAP controllers with embedded compression for large test data volume.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Machine learning based test pattern analysis for localizing critical power activity areas.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Endurance management for resistive Logic-In-Memory computing architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Effects of cell shapes on the routability of Digital Microfluidic Biochips.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Data flow testing for virtual prototypes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Identification of Efficient Clustering Techniques for Test Power Activity on the Layout.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Exact routing for micro-electrode-dot-array digital microfluidic biochips.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Enhancing robustness of sequential circuits using application-specific knowledge and formal methods.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Complexity of reversible circuits and their quantum implementations.
Theor. Comput. Sci., 2016

QMDDs: Efficient Quantum Function Representation and Manipulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Ancilla-free synthesis of large reversible functions using binary decision diagrams.
J. Symb. Comput., 2016

Embedding of Large Boolean Functions for Reversible Logic.
JETC, 2016

Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits.
JETC, 2016

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability.
JETC, 2016

Analyzing Inconsistencies in UML/OCL Models.
Journal of Circuits, Systems, and Computers, 2016

SyReC: A hardware description language for the specification and synthesis of reversible circuits.
Integration, 2016

Verifying the structure and behavior in UML/OCL models using satisfiability solvers.
IET Cyper-Phys. Syst.: Theory & Appl., 2016

Hardware/Software Co-Visualization on the Electronic System Level Using SystemC.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

From reversible logic to quantum circuits: Logic design for an emerging technology.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Ground setting properties for an efficient translation of OCL in SMT-based model finding.
Proceedings of the ACM/IEEE 19th International Conference on Model Driven Engineering Languages and Systems, 2016

Integrating an SMT-Based ModelFinder into USE.
Proceedings of the 13th Workshop on Model-Driven Engineering, 2016

Frame conditions in symbolic representations of UML/OCL models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models.
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Symbolic Error Metric Determination for Approximate Computing.
Proceedings of the 19th GI/ITG/GMM Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2016

Model-Based Specification and Refinement for Cyber-Physical Systems.
Proceedings of the Dynamics in Logistics, 2016

Fault Detection in Parity Preserving Reversible Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Generating and checking control logic in the HDL-based design of reversible circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Towards a model-based verification methodology for Complex Swarm Systems (Invited paper).
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Exploring superior structural materials using multi-objective optimization and formal techniques.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

An improved gate library for logic synthesis of optical circuits.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Guided lightweight Software test qualification for IP integration using Virtual Prototypes.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

From biochips to quantum circuits: computer-aided design for emerging technologies.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Compiled symbolic simulation for systemC.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximation-aware rewriting of AIGs for error tolerant applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm.
Proceedings of the Genetic and Evolutionary Computation Conference, 2016

Equivalence checking using Gröbner bases.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Change impact analysis for hardware designs from natural language to system level.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers.
Proceedings of the 21th IEEE European Test Symposium, 2016

Multi-objective BDD optimization for RRAM based circuit design.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Formal verification of integer multipliers by combining Gröbner basis with logic reduction.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Towards formal verification of real-world SystemC TLM peripheral models - a case study.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Quantitative timing analysis of UML activity diagrams using statistical model checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

An MIG-based compiler for programmable logic-in-memory architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Precise error determination of approximated components in sequential circuits with model checking.
Proceedings of the 53rd Annual Design Automation Conference, 2016

ParCoSS: Efficient Parallelized Compiled Symbolic Simulation.
Proceedings of the Computer Aided Verification - 28th International Conference, 2016

Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

BDD minimization for approximate computing.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications.
Sensors, 2015

Incorporating user preferences in many-objective optimization using relation ε-preferred.
Natural Computing, 2015

Scalable One-Pass Synthesis for Digital Microfluidic Biochips.
IEEE Design & Test, 2015

Benefits of illustrations and videos for technical documentations.
Computers in Human Behavior, 2015

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits.
Proceedings of the 28th International Conference on VLSI Design, 2015

Reversible circuit rewriting with simulated annealing.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

Coverage of OCL Operation Specifications and Invariants.
Proceedings of the Tests and Proofs - 9th International Conference, 2015

Development of Consistent Formal Models.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Design and Synthesis of Reversible Circuits using Hardware Description Languages.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Analyzing and Simulating Time Descriptions from UML/MARTE CCSL.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Behavior Driven Development for Tests and Verification.
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015

Ensuring safety and reliability of IP-based system design - A container approach.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Envisioning self-verification of electronic systems.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition.
Proceedings of the Reversible Computation - 7th International Conference, 2015

Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses.
Proceedings of the 12th Workshop on Model-Driven Engineering, 2015

Checking concurrent behavior in UML/OCL models.
Proceedings of the 18th ACM/IEEE International Conference on Model Driven Engineering Languages and Systems, 2015

Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2015

Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Formal Methods for Emerging Technologies.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A General and Exact Routing Methodology for Digital Microfluidic Biochips.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Reversible computation.
Proceedings of the Sixth International Green and Sustainable Computing Conference, 2015

Multi-Objective BDD Optimization with Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015

Reverse Engineering with Simulation Graphs.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Leveraging the Analysis for Invariant Independence in Formal System Models.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Verification-Driven Design Across Abstraction Levels: A Case Study.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Contradiction Analysis for Inconsistent Formal Models.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Requirement Phrasing Assistance Using Automatic Quality Assessment.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Automated feature localization for dynamically generated SystemC designs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A generic representation of CCSL time constraints for UML/MARTE models.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Verifying SystemC using stateful symbolic simulation.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules.
Proceedings of the Automated Technology for Verification and Analysis, 2015

Reverse BDD-based synthesis for splitter-free optical circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

Formal Specification Level - Concepts, Methods, and Algorithms.
Springer, ISBN: 978-3-319-08698-9, 2015

2014
An Approach to Reversible Logic Synthesis Using Input and Output Permutations.
Trans. Computational Science, 2014

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic.
Trans. Computational Science, 2014

Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Considering nearest neighbor constraints of quantum circuits at the reversible circuit level.
Quantum Information Processing, 2014

Introduction to the Special Issue on Reversible Computation.
JETC, 2014

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques.
it - Information Technology, 2014

Testing integrated circuits.
it - Information Technology, 2014

Upper bounds for reversible circuits based on Young subgroups.
Inf. Process. Lett., 2014

Trading off circuit lines and gate costs in the synthesis of reversible logic.
Integration, 2014

Behaviour Driven Development for Tests and Verification.
Proceedings of the Tests and Proofs - 8th International Conference, 2014

iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries.
Proceedings of the 8th International Workshop on Semantic Evaluation, 2014

Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Validating SystemC Implementations Against Their Formal Specifications.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Self-Verification as the Key Technology for Next Generation Electronic Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

RevVis: Visualization of Structures and Properties in Reversible Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Equivalence Checking in Multi-level Quantum Systems.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Mapping NCV Circuits to Optimized Clifford+T Circuits.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Quantum Circuit Optimization by Hadamard Gate Reduction.
Proceedings of the Reversible Computation - 6th International Conference, 2014

Funktionale Abdeckungsanalyse von C-Programmen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Formale Methoden für Alle.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

A Logic for Cardinality Constraints (Extended Abstract).
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Safe IP Integration Using Container Modules.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0".
Proceedings of the Advances in Production Management Systems. Innovative and Knowledge-Based Production Management in a Global-Local World, 2014

Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL.
Proceedings of the 2014 19th International Conference on Engineering of Complex Computer Systems, 2014

Exact routing for digital microfluidic biochips with temporary blockages.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automated and quality-driven requirements engineering.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Automating the translation of assertions using natural language processing techniques.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Automatic refinement checking for formal system models.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

MetaSMT: a unified interface to SMT-LIB2.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Verifying consistency between activity diagrams and their corresponding OCL contracts.
Proceedings of the 2014 Forum on Specification and Design Languages, 2014

Optimization-based multiple target test generation for highly compacted test sets.
Proceedings of the 19th IEEE European Test Symposium, 2014

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Optimizing DD-based synthesis of reversible circuits using negative control lines.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

Towards verifying determinism of SystemC designs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Panel: Future SoC verification methodology: UVM evolution or revolution?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


Exact One-pass Synthesis of Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Optimal SWAP gate insertion for nearest neighbor quantum circuits.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Efficient synthesis of quantum circuits implementing clifford group operations.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits.
Multiple-Valued Logic and Soft Computing, 2013

A formal model for embedded brain reading.
Industrial Robot, 2013

Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis.
ECEASST, 2013

On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Exploiting Negative Control Lines in the Optimization of Reversible Circuits.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Reducing the Depth of Quantum Circuits Using Additional Circuit Lines.
Proceedings of the Reversible Computation - 5th International Conference, 2013

Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2013

PASSAT 2.0: A multi-functional SAT-based testing framework.
Proceedings of the 14th Latin American Test Workshop, 2013

Data extraction from SystemC designs using debug symbols and the SystemC API.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Debugging of Reversible Circuits Using pDDs.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Exact Template Matching Using Boolean Satisfiability.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred.
Proceedings of the IJCCI 2013, 2013

Grammar-based program generation based on model finding.
Proceedings of the 8th International Design and Test Symposium, 2013

An evolutionary approach to reversible logic synthesis using output permutation.
Proceedings of the 8th International Design and Test Symposium, 2013

Towards automatic scenario generation from coverage information.
Proceedings of the 8th International Workshop on Automation of Software Test, 2013

Improved SAT-based ATPG: more constraints, better compaction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung.
Proceedings of the Informatik 2013, 2013

Minimal Stimuli Generation in Simulation-Based Verification.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Cone of Influence Analysis at the Electronic System Level Using Machine Learning.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Hardware-Software Co-Visualization: Developing systems in the holodeck.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Towards a generic verification methodology for system models.
Proceedings of the Design, Automation and Test in Europe, 2013

Determining relevant model elements for the verification of UML/OCL specifications.
Proceedings of the Design, Automation and Test in Europe, 2013

Scalable fault localization for SystemC TLM designs.
Proceedings of the Design, Automation and Test in Europe, 2013

Verifying SystemC using an intermediate verification language and symbolic simulation.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Improving the mapping of reversible circuits to quantum circuits using multiple target lines.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Automatic TLM Fault Localization for SystemC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

RevKit: A Toolkit for Reversible Circuit Design.
Multiple-Valued Logic and Soft Computing, 2012

Foreword: Special Issue on Reversible Computation.
Multiple-Valued Logic and Soft Computing, 2012

A Highly Fault-Efficient SAT-Based ATPG Flow.
IEEE Design & Test of Computers, 2012

Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper).
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Assisted Behavior Driven Development Using Natural Language Processing.
Proceedings of the Objects, Models, Components, Patterns - 50th International Conference, 2012

Using πDDs in the Design of Reversible Circuits.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams.
Proceedings of the Reversible Computation, 4th International Workshop, 2012

CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2012

Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

CRAVE: An advanced constrained random verification environment for SystemC.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

A Synthesis Flow for Sequential Reversible Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

From Requirements and Scenarios to ESL Design in SystemC.
Proceedings of the International Symposium on Electronic System Design, 2012

Synthesis of Reversible Circuits Using Decision Diagrams.
Proceedings of the International Symposium on Electronic System Design, 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Generating formal system models from natural language descriptions.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Behavior Driven Development for circuit design and verification.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Completeness-Driven Development.
Proceedings of the Graph Transformations - 6th International Conference, 2012

Complete and effective robustness checking by means of interpolation.
Proceedings of the Formal Methods in Computer-Aided Design, 2012

Localizing features of ESL models for design understanding.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Formal Specification Level.
Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

Formal Specification Level: Towards verification-driven design based on natural language processing.
Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

Coverage-Driven Stimuli Generation.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A new SAT-based ATPG for generating highly compacted test sets.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Debugging of inconsistent UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Automatic design of low-power encoders using reversible circuit synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Eliminating invariants in UML/OCL models.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A guiding coverage metric for formal verification.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

The system verification methodology for advanced TLM verification.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

Synthesis of reversible circuits with minimal lines for large functions.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

High Quality Test Pattern Generation and Boolean Satisfiability.
Springer, ISBN: 978-1-4419-9975-7, 2012

2011
Effective Robustness Analysis Using Bounded Model Checking Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Synthesis of quantum circuits for linear nearest neighbor architectures.
Quantum Information Processing, 2011

Debugging reversible circuits.
Integration, 2011

Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models.
Proceedings of the Tests and Proofs - 5th International Conference, 2011

RevKit: An Open Source Toolkit for the Design of Reversible Circuits.
Proceedings of the Reversible Computation - Third International Workshop, 2011

Designing a RISC CPU in Reversible Logic.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Towards Automatic Property Generation for the Formal Verification of Bus Bridges.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2011

ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops, 2011

Designing a RISC CPU in Reversible Logic.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Simulation-based equivalence checking between SystemC models at different levels of abstraction.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

metaSMT: Focus on Your Application not on Solver Integration.
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011

Efficient realization of control logic in reversible circuits.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Analyzing dependability measures at the Electronic System Level.
Proceedings of the 2011 Forum on Specification & Design Languages, 2011

Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms.
Proceedings of the Applications of Evolutionary Computation, 2011

Automatic property generation for the formal verification of bus bridges.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

TLM protocol compliance checking at the Electronic System Level.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Determining the minimal number of lines for large reversible circuits.
Proceedings of the Design, Automation and Test in Europe, 2011

Verifying dynamic aspects of UML models.
Proceedings of the Design, Automation and Test in Europe, 2011

As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization.
Proceedings of the Design, Automation and Test in Europe, 2011

Improved Fault Diagnosis for Reversible Circuits.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Incremental Solving Techniques for SAT-based ATPG.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Synthese reversibler Logik (Synthesizing Reversible Logic).
it - Information Technology, 2010

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).
it - Information Technology, 2010

BDD-Based Synthesis of Reversible Logic.
Int. J. of Applied Metaheuristic Computing, 2010

MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics.
J. Electronic Testing, 2010

Towards Fully Automatic Synthesis of Embedded Software.
Embedded Systems Letters, 2010

Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic.
Electr. Notes Theor. Comput. Sci., 2010

Automatic Fault Localization for SystemC TLM Designs.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Towards Unifying Localization and Explanation for Automated Debugging.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

Proving transaction and system-level properties of untimed SystemC TLM designs.
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Verifying UML/OCL Models Using Boolean Satisfiability.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2010

Reducing Reversible Circuit Cost by Adding Lines.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Efficient Simulation-Based Debugging of Reversible Logic.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

Using QBF to increase accuracy of SAT-based debugging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

SAT-based ATPG for reversible circuits.
Proceedings of the 5th International Design and Test Workshop, 2010

Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition.
Proceedings of the 5th International Design and Test Workshop, 2010

Polynomial datapath optimization using constraint solving and formal modelling.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Towards analyzing functional coverage in SystemC TLM property checking.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

Enhancing debugging of multiple missing control errors in reversible logic.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Automatic Fault Localization for Programmable Logic Controllers.
Proceedings of the FORMS/FORMAT 2010, 2010

SyReC: A Programming Language for Synthesis of Reversible Circuits.
Proceedings of the 2010 Forum on specification & Design Languages, 2010

Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs.
Proceedings of the 15th European Test Symposium, 2010

RobuCheck: A Robustness Checker for Digital Circuits.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Window optimization of reversible and quantum circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Synthesizing multiplier in reversible logic.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A better-than-worst-case robustness measure.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Formal verification meets robustness checking - Techniques and challenges.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Verifying UML/OCL models using Boolean satisfiability.
Proceedings of the Design, Automation and Test in Europe, 2010

Reducing the number of lines in reversible circuits.
Proceedings of the 47th Design Automation Conference, 2010

Quality-Driven SystemC Design
Springer, ISBN: 978-90-481-3630-8, 2010

Towards a Design Flow for Reversible Logic.
Springer, ISBN: 978-90-481-9578-7, 2010

Debugging at the Electronic System Level.
Springer, ISBN: 978-90-481-9254-0, 2010

2009
Non-Clausal SAT and ATPG.
Proceedings of the Handbook of Satisfiability, 2009

Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Exact Synthesis of Elementary Quantum Gate Circuits.
Multiple-Valued Logic and Soft Computing, 2009

Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation).
it - Information Technology, 2009

Advanced verification by automatic property generation.
IET Computers & Digital Techniques, 2009

Weighted A* search - unifying view and application.
Artif. Intell., 2009

Reversible Logic Synthesis with Output Permutation.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Automatic debugging of System-on-a-Chip designs.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

WoLFram- A Word Level Framework for Formal Verification.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Induction-Based Formal Verification of SystemC TLM Designs.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Equivalence Checking of Reversible Circuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Increasing the Accuracy of SAT-based Debugging.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Equivalence Checking of Reversible Circuits.
Proceedings of the ISMVL 2009, 2009

Evaluation of Cardinality Constraints on SMT-Based Debugging.
Proceedings of the ISMVL 2009, 2009

Approximate BDD Minimization by Weighted A.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Timing Arc based logic analysis for false noise reduction.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Contradictory antecedent debugging in bounded model checking.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

SMT-based stimuli generation in the SystemC Verification library.
Proceedings of the Forum on specification and Design Languages, 2009

Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques.
Proceedings of the 14th IEEE European Test Symposium, 2009

Robustness Check for Multiple Faults Using Formal Techniques.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A fast untestability proof for SAT-based ATPG.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Debugging of Toffoli networks.
Proceedings of the Design, Automation and Test in Europe, 2009

Increasing the accuracy of SAT-based debugging.
Proceedings of the Design, Automation and Test in Europe, 2009

Property analysis and design understanding.
Proceedings of the Design, Automation and Test in Europe, 2009

Overcoming limitations of the SystemC data introspection.
Proceedings of the Design, Automation and Test in Europe, 2009

SWORD - Module-based SAT Solving.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

Formal Verification of Abstract SystemC Models.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers.
Proceedings of the Algorithms and Applications for Next Generation SAT Solvers, 08.11., 2009

BDD-based synthesis of reversible logic for large functions.
Proceedings of the 46th Design Automation Conference, 2009

Computing bounds for fault tolerance using formal techniques.
Proceedings of the 46th Design Automation Conference, 2009

Speeding up SAT-Based ATPG Using Dynamic Clause Activation.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Test Pattern Generation using Boolean Proof Engines.
Springer, ISBN: 978-90-481-2359-9, 2009

2008
Analyzing Functional Coverage in Bounded Model Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Automatic Fault Localization for Property Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Logic Minimization and Testability of 2-SPP Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Modeling and proving functional completeness in formal verification of counting heads.
STTT, 2008

Improved SAT-based Reachability Analysis with Observability Don't Cares.
JSAT, 2008

Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

Debugging Design Errors by Using Unsatisfiable Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Adaptive Branch and Bound Using SAT to Estimate False Crosstalk.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Basis for Formal Robustness Checking.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

RevLib: An Online Resource for Reversible Functions and Reversible Circuits.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Comparative Study by Solving the Test Compaction Problem.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Using unsatisfiable cores to debug multiple design errors.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Debugging Contradictory Constraints in Constraint-Based Random Simulation.
Proceedings of the Languages for Embedded Systems and their Applications, 2008

Contradiction Analysis for Constraint-based Random Simulation.
Proceedings of the Forum on specification and Design Languages, 2008

Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Incremental SAT Instance Generation for SAT-based ATPG.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

Automatic Generation of Complex Properties for Hardware Designs.
Proceedings of the Design, Automation and Test in Europe, 2008

Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2008

SAT-based Automatic Test Pattern Generation.
Proceedings of the Evolutionary Test Generation, 24.08. - 29.08.2008, 2008

Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robustness and usability in modern design flows.
Springer, ISBN: 978-1-4020-6535-4, 2008

2007
Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems).
it - Information Technology, 2007

Preface.
Electr. Notes Theor. Comput. Sci., 2007

Reusing Learned Information in SAT-based ATPG.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

SWORD: A SAT like Prover Using Word Level Information.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

SWORD: A SAT like prover using word level information.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Co-synthesis of custom on-chip bus and memory for MPSoC architectures.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
Proceedings of the 5th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2007), May 30, 2007

Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Formal Verification on the Word Level using SAT-like Proof Techniques.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2007

Improving the Quality of Bounded Model Checking by Means of Coverage Estimation.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Visualization of SystemC Designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SAT-based ATPG for Path Delay Faults in Sequential Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?.
Proceedings of the ICSOFT 2007, 2007

Improvements for constraint solving in the systemc verification library.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Exact sat-based toffoli network synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An Integrated SystemC Debugging Environment.
Proceedings of the Forum on specification and Design Languages, 2007

Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques.
Proceedings of the Forum on specification and Design Languages, 2007

Proving Completeness of Properties in Formal Verification of Counting Heads for Railways.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

On the Construction of Small Fully Testable Circuits with Low Depth.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Instance Generation for SAT-based ATPG.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Estimating functional coverage in bounded model checking.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Minimizing the number of paths in BDDs: Theory and algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Effect of improved lower bounds in dynamic BDD reordering.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Testability of SPP Three-Level Logic Networks in Static Fault Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

An Integrated Approach for Combining BDD and SAT Provers.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Technical Documentation of Software and Hardware in Embedded Systems.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Automatic Test Pattern Generation.
Proceedings of the Formal Methods for Hardware Verification, 2006

Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

SAT-based Calculation of Source Code Coverage for BMC.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2006

A Framework for Quasi-exact Optimization Using Relaxed Best-First Search.
Proceedings of the KI 2006: Advances in Artificial Intelligence, 2006

System Exploration of SystemC Designs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Efficiency of Multi-Valued Encoding in SAT-based ATPG.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Integrating observability don't cares in all-solution SAT solvers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

On the sensitivity of BDDs with respect to path-related objective functions.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Automatic Fault Localization for Property Checking.
Proceedings of the Hardware and Software, 2006

HW/SW co-verification of embedded systems using bounded model checking.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion.
Proceedings of the Applications of Evolutionary Computing, 2006

Robust Multi-Objective Optimization in High Dimensional Spaces.
Proceedings of the Evolutionary Multi-Criterion Optimization, 4th International Conference, 2006

On the relation between simulation-based and SAT-based diagnosis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Avoiding false negatives in formal verification for protocol-driven blocks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Efficient minimization of fully testable 2-SPP networks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Generic Implementation of Multi-Valued Logic Decision Diagram Packages.
Multiple-Valued Logic and Soft Computing, 2005

Exact BDD Minimization for Path-Related Objective Functions.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

SyCE: An Integrated Environment for System Design in SystemC.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Post-Verification Debugging of Hierarchical Designs.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Quasi-Exact BDD Minimization Using Relaxed Best-First Search.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Controlling the Memory During Manipulation of Word-Level Decision Diagrams.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

CheckSyC: an efficient property checker for RTL SystemC designs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Post-verification debugging of hierarchical designs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Utilizing don't care states in SAT-based bounded sequential problems.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors.
Proceedings of the INFORMATIK 2005, 2005

Acceleration of SAT-Based Iterative Property Checking.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Bridging fault testability of BDD circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Lower bounds for dynamic BDD reordering.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Advanced BDD optimization.
Springer, ISBN: 978-0-387-25453-1, 2005

2004
Synthesis of fully testable circuits from BDDs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Method for Construction of Recursive Algorithms for Reed- Muller-Fourier Polarity Matrices Calculation.
Multiple-Valued Logic and Soft Computing, 2004

Towards Formal Verification on the System Level.
Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

Debugging Sequential Circuits Using Boolean Satisfiability.
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004

Checkers for SystemC designs.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

A Tight Lower Bound for Dynamic BDD Reordering.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Efficient (Non-)Reachability Analysis of Counterexamples.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Using Synthesis Techniques in SAT Solvers.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Algorithms for Taylor Expansion Diagrams.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Placement and routing optimization for circuits derived from BDDs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Debugging sequential circuits using Boolean satisfiability.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Disjoint Sum of Product Minimization by Evolutionary Algorithms.
Proceedings of the Applications of Evolutionary Computing, 2004

BDD Circuit Optimization for Path Delay Fault Testability.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Managing Don't Cares in Boolean Satisfiability.
Proceedings of the 2004 Design, 2004

Improving simulation-based verification by means of formal methods.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Combining ordered best-first search with branch and bound for exact BDD minimization.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Minimization of the expected path length in BDDs based on local changes.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
An improved branch and bound algorithm for exact BDD minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Exact Routing with Search Space Reduction.
IEEE Trans. Computers, 2003

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams.
IEEE Trans. Computers, 2003

Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC.
it - Information Technology, 2003

Polynomial Formal Verification of Multipliers.
Formal Methods in System Design, 2003

Exploration of Sequential Depth by Evolutionary Algorithms.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Exploration of Sequential Depth by Evolutionary Algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Stuck-At-Fault Testability of SPP Three-Level Logic Forms.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Testability of SPP Three-Level Logic Networks.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Finding Good Counter-Examples to Aid Design Verification.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Augmented Sifting of Multiple-Valued Decision Diagrams.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Modeling Multi-Valued Circuits in SystemC.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Formal verification of LTL formulas for SystemC designs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Synthesizing checkers for on-line verification of System-on-Chip designs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

BDD-based verification of scalable designs.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

MuTaTe: an efficient design for testability technique for multiplexor based circuits.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Efficient Automatic Visualization of SystemC Designs.
Proceedings of the Forum on specification and Design Languages, 2003

GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages.
Proceedings of the Applications of Evolutionary Computing, 2003

Fast Heuristics for the Edge Coloring of Large Graphs.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Combination of Lower Bounds in Exact BDD Minimization.
Proceedings of the 2003 Design, 2003

BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms.
Proceedings of the 21st IASTED International Multi-Conference on Applied Informatics (AI 2003), 2003

2002
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.
VLSI Design, 2002

Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts.
VLSI Design, 2002

Minimization of Word-Level Decision Diagrams.
Integration, 2002

Heuristic Learning Based on Genetic Programming.
Genetic Programming and Evolvable Machines, 2002

RTL-Datapath Verification using Integer Linear Programming.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Symbolic Simulation of Algorithms Specified in HDL.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Implementation and Visualization of a BDD Package in JAVA.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2002

Low Power Optimization Techniques for BDD Mapped Finite State Machines.
IWLS, 2002

Multi-Output Timed Shannon Circuits.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

On the Relation between SAT and BDDs for Equivalence Checking.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

On the Construction of Multiple-Valued Decision Diagrams.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Evaluation of Static Variable Ordering Heuristics for MDD Construction.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Switching activity estimation of finite state machines for low power synthesis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Crossing Reduction by Windows Optimization.
Proceedings of the Graph Drawing, 10th International Symposium, 2002

Decision Diagram Optimization Using Copy Properties.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Recursive Bi-Partitioning of Netlists for Large Number of Partitions.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Reachability Analysis for Formal Verification of SystemC.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2001
Using lower bounds during dynamic BDD minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Decision Diagram Method for Calculation of Pruned Walsh Transform.
IEEE Trans. Computers, 2001

Binary decision diagrams in theory and practice.
STTT, 2001

Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment).
it+ti - Informationstechnik und Technische Informatik, 2001

History-based dynamic BDD minimization.
Integration, 2001

Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
J. Electronic Testing, 2001

Performance Driven Optimization for MUX based FPGAs.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Implementation of Read- k-times BDDs on Top of Standard BDD Packages.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

GateComp: Equivalence Checking in CVE.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Selection of Efficient Re-Ordering Heuristics for MDD Construction.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.
Proceedings of the SOC Design Methodologies, 2001

Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.
Proceedings of the Computational Intelligence, 2001

Heuristic Learning Based on Genetic Programming.
Proceedings of the Genetic Programming, 4th European Conference, 2001

Multi-objective Optimisation Based on Relation Favour.
Proceedings of the Evolutionary Multi-Criterion Optimization, 2001

Minimization of OPKFDDs Using Genetic Algorithms.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Level Assignment for Displaying Combinational Logic.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Spectral decision diagrams using graph transformations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Low power optimization technique for BDD mapped circuits.
Proceedings of ASP-DAC 2001, 2001

Utilizing High-Level Information for Formal Hardware Verification.
Proceedings of the Advanced Computer Systems, Eighth International Conference, 2001

Tabular Techniques for MV Logic.
Proceedings of the Advanced Computer Systems, Eighth International Conference, 2001

Spectral techniques in VLSI CAD.
Kluwer, ISBN: 978-0-7923-7433-6, 2001

2000
Fast exact minimization of BDD's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

On the computational power of linearly transformed BDDs.
Inf. Process. Lett., 2000

Boolean function representation and spectral characterization using AND/OR graphs.
Integration, 2000

OKFDD minimization by genetic algorithms with application to circuit design.
Integration, 2000

Verification of Designs Containing Black Boxes.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

A Method for Approximate Equivalence Checking.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Dynamic Re-Encoding During MDD Minimization.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Lower Bound Sifting for MDDs.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

MDD-Based Synthesis of Multi-Valued Logic Networks.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Computation of Spectral Information from Logic Netlists.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Optimization of sequential verification by history-based dynamic minimization of BDDs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Minimization of Ordered Pseudo Kronecker Decision Diagrams.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Specialized Hardware for Implementation of Evolutionary Algorithms.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

Improving EAs for Sequencing Problems.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

Verification of Designs Containing Black Boxes.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Testability of Circuits Derived from Lattice Diagrams.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
Evolutionary Algorithms for VLSI CAD [book Review].
IEEE Trans. Evolutionary Computation, 1999

BDD minimization using symmetries.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Preudo-Kronecker Expressions for Symmetric Functions.
IEEE Trans. Computers, 1999

Grouping Heuristics for Word-Level Decision Diagrams.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 1999

Exact channel routing using symbolic representation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Creating hard problem instances in logic synthesis using exact minimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Minimization of BDDs using linear transformations based on evolutionary techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Grouping heuristics for word-level decision diagrams.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of experiments in CAD: context and new data sets for ISCAS'99.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

History-Based Dynamic Minimization During BDD Construction.
Proceedings of the VLSI: Systems on a Chip, 1999

Synthesis of Pseudo Kronecker Lattice Diagrams.
Proceedings of the IEEE International Conference On Computer Design, 1999

Efficient manipulation algorithms for linearly transformed BDDs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Efficient Graph Coloring by Evolutionary Algorithms.
Proceedings of the Computational Intelligence, 1999

Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes.
Proceedings of the Computational Intelligence, 1999

Generic Implementation of DD Packages in MVL.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Generation of Optimal Universal Logic Modules.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Checking Integrity During Dynamic Reordering in Decision Diagrams.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities.
Proceedings of the 1999 Design, 1999

Formal Verification of Word-Level Specifications.
Proceedings of the 1999 Design, 1999

Using Lower Bounds During Dynamic BDD Minimization.
Proceedings of the 36th Conference on Design Automation, 1999

Power Consumption in XOR-Based Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Minimization of Free BDDs.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Exploiting Don't Caers During Data Sequencing using Genetic Algorithms.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
The complexity of the inclusion operation on OFDD's.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

On Variable Ordering and Decomposition Type Choice in OKFDDs.
IEEE Trans. Computers, 1998

Verifying Integrity of Decision Diagrams.
Proceedings of the Computer Safety, 1998

Implementing a Multiple-Valued Decision Diagram Package.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Linear Transformations and Exact Minimization of BDDs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Dynamic Minimization of Word-Level Decision Diagrams.
Proceedings of the 1998 Design, 1998

Fast Exact Minimization of BDDs.
Proceedings of the 35th Conference on Design Automation, 1998

ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions.
Proceedings of the ASP-DAC '98, 1998

Manipulation of *BMDs.
Proceedings of the ASP-DAC '98, 1998

Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen.
Leitfäden der Informatik, Teubner, ISBN: 978-3-519-02149-0, 1998

Binary Decision Diagrams - Theory and Implementation.
Springer, ISBN: 978-0-7923-8193-8, 1998

1997
On the Expressive Power of OKFDDs.
Formal Methods in System Design, 1997

The K*BMD: A Verification Data Structure.
IEEE Design & Test of Computers, 1997

Polynomial Formal Verification of Multipliers.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Pseudo Kronecker Expressions for Symmetric Functions.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

(Quasi-) Linear Path Delay Fault Tests for Adders.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Manipulation Algorithms for K*BMDs.
Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 1997

Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Fault Simulation in Sequential Multi-Valued Logic Networks.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Functional simulation using binary decision diagrams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast and efficient construction of BDDs by reordering based synthesis.
Proceedings of the European Design and Test Conference, 1997

Testability of 2-level AND/EXOR circuits.
Proceedings of the European Design and Test Conference, 1997

Learning heuristics for OKFDD minimization by evolutionary algorithms.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

On the representational power of bit-level and word-level decision diagrams.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Ordered Kronecker functional decision diagrams und ihre Anwendung.
PhD thesis, 1996

Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.
IEEE Trans. Computers, 1996

Learning Heuristics for OBDD Minimization by Evolutionary Algorithms.
Proceedings of the Parallel Problem Solving from Nature, 1996

Verification of Multi-Valued Logic Networks.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

MORE: an alternative implementation of BDD packages by multi-operand synthesis.
Proceedings of the conference on European design automation, 1996

K*BMDs: A New Data Structure for Verification.
Proceedings of the 1996 European Design and Test Conference, 1996

A Fast Optimal Robust Path Delay Fault Testable Adder.
Proceedings of the 1996 European Design and Test Conference, 1996

AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
On the generation of area-time optimal testable adders.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

A Genetic Algorithm for Decomposition Type Choice in OKFDDs.
International Journal on Artificial Intelligence Tools, 1995

On the Relation between BDDs and FDDs.
Inf. Comput., 1995

On local transformations and path delay fault testability.
J. Electronic Testing, 1995

On the application of local circuit transformations with special emphasis on path delay fault testability.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On the Relation Betwen BDDs and FDDs.
Proceedings of the LATIN '95: Theoretical Informatics, 1995

Random Pattern Fault Simulation in Multi-Valued Circuits.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Dynamic minimization of OKFDDs.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

OKFDDs versus OBDDs and OFDDs.
Proceedings of the Automata, Languages and Programming, 22nd International Colloquium, 1995

Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
Proceedings of the 1995 European Design and Test Conference, 1995

Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams.
Proceedings of the 1995 European Design and Test Conference, 1995

How many decomposition types do we need? [decision diagrams].
Proceedings of the 1995 European Design and Test Conference, 1995

Learning heuristics by genetic algorithms.
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

Fast OFDD based minimization of fixed polarity Reed-Muller expressions.
Proceedings of the Proceedings EURO-DAC'94, 1994

BiTeS: a BDD based test pattern generator for strong robust path delay faults.
Proceedings of the Proceedings EURO-DAC'94, 1994

Testability of Circuits Derived from Functional Decision Diagrams.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
Proceedings of the 31st Conference on Design Automation, 1994

1993
On the implementation of an efficient performance driven generator for conditional-sum-adders.
Proceedings of the European Design Automation Conference 1993, 1993

1992
A time optimal robust path-delay-fault self-testable adder.
Proceedings of the conference on European design automation, 1992


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