Peter J. Ashenden

According to our database1, Peter J. Ashenden authored at least 17 papers between 1987 and 2004.

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Bibliography

2004
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link.
IEEE Micro, 2004

Policies and procedures - who needs them?
IEEE Des. Test Comput., 2004

Programming Models for Hybrid CPU/FPGA Chips.
Computer, 2004

Improving Design and Verification Productivity with VHDL-200x.
Proceedings of the 2004 Design, 2004

2003
VHDL-200X: The Next Revision.
IEEE Des. Test Comput., 2003

Boundary Scan Test Standards.
IEEE Des. Test Comput., 2003

2002
Standards: Technical activities in Accellera.
IEEE Des. Test Comput., 2002

What Makes a Good Standard?
IEEE Des. Test Comput., 2002

The designer's guide to VHDL, 2nd Edition.
The Morgan Kaufmann series in systems on silicon, Kaufmann, ISBN: 1558606742, 2002

2001
VHDL Standards.
IEEE Des. Test Comput., 2001

1999
Principles for Language Extensions to VHDL to Support High-Level Modeling.
VLSI Design, 1999

Protected Shared Variables in VHDL: IEEE Standard 1076a.
IEEE Des. Test Comput., 1999

1998
SUAVE: Extending VHDL to Improve Data Modeling Support.
IEEE Des. Test Comput., 1998

Extensions to VHDL for Abstraction of Concurrency and Communication.
Proceedings of the MASCOTS 1998, 1998

1994
Execution of VHDL Models Using Parallel Discrete Event Simulation Algorithms.
VLSI Design, 1994

1988
A Behavioural Specification of Cache Coherence.
Aust. Comput. J., 1988

1987
The Leopard workstation project.
SIGARCH Comput. Archit. News, 1987


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