David Andrews

Orcid: 0000-0003-1464-7107

Affiliations:
  • University of Arkansas, Computer Science and Computer Engineering Department, Fayetteville, AR, USA
  • University of Kansas, Lawrence, KS, USA (2000 - 2008)
  • University of Arkansas, Fayetteville, AR, USA (1992 - 2000)
  • Syracuse University, NY, USA (PhD 1992)


According to our database1, David Andrews authored at least 65 papers between 1991 and 2023.

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Bibliography

2023
FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Accelerating LSTM-Based High-Rate Dynamic System Models.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm.
IACR Cryptol. ePrint Arch., 2022

High-Rate Machine Learning for Forecasting Time-Series Signals.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

A Runtime Programmable Accelerator for Convolutional and Multilayer Perceptron Neural Networks on FPGA.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2022

2021
Power-based Side Channel Attack Analysis on PQC Algorithms.
IACR Cryptol. ePrint Arch., 2021

A Customizable Domain-Specific Memory-Centric FPGA Overlay for Machine Learning Applications.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
An FPGA-Based Upper-Limb Rehabilitation Device for Gesture Recognition and Motion Evaluation Using Multi-Task Recurrent Neural Networks.
Proceedings of the International Conference on Field-Programmable Technology, 2020

SPAR-2: A SIMD Processor Array for Machine Learning in IoT Devices.
Proceedings of the 3rd International Conference on Data Intelligence and Security, 2020

FPGA-Based Gesture Recognition with Capacitive Sensor Array using Recurrent Neural Networks.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology.
J. Signal Process. Syst., 2019

A Library of FSM-based Floating-Point Arithmetic Functions on FPGAs.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

2018
Transparent Acceleration of Image Processing Kernels on FPGA-Attached Hybrid Memory Cube Computers.
Proceedings of the International Conference on Field-Programmable Technology, 2018

Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

An FPGA/HMC-Based Accelerator for Resolution Proof Checking.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

FPGAVirt: A Novel Virtualization Framework for FPGAs in the Cloud.
Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2016
A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators.
CoRR, 2016

Programming models for reconfigurable manycore systems.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Breeze computing: A just in time (JIT) approach for virtualizing FPGAs in the cloud.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

OOGen: An Automated Generation Tool for Custom MPSoC Architectures Based on Object-Oriented Programming Methods.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Just In Time Assembly of Accelerators.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Run time interpretation for creating custom accelerators.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Archborn: an open source tool for automated generation of chip heterogeneous multiprocessor architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A run time interpretation approach for creating custom accelerators.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Automatic support for multi-module parallelism from computational patterns.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A Flexible Multilayer Perceptron Co-processor for FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Operating Systems Research for Reconfigurable Computing.
IEEE Micro, 2014

Achieving portability and efficiency over chip heterogeneous multiprocessor systems.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

On energy efficiency and amdahl's law in FPGA based chip heterogeneous multiprocessor systems (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Modular Design of Fully Pipelined Reduction Circuits on FPGAs.
IEEE Trans. Parallel Distributed Syst., 2013

2012
Developing application-specific multiprocessor platforms on FPGAs.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Automating the design of mLUT MPSoPC FPGAs in the cloud.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Scalable Memory Hierarchies for Embedded Manycore Systems.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
A Streaming High-Throughput Linear Sorter System with Contention Buffering.
Int. J. Reconfigurable Comput., 2011

Creating HW/SW co-designed MPSoPC's from high level programming models.
Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

2010
Operating System Structures for Multiprocessor Systems on Programmable Chip.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

A configurable high-throughput linear sorter system.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Modular design of fully pipelined accumulators.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Configurable Processor Architectures: History and Trends.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

2009
Hardware Microkernels for Heterogeneous Manycore Systems.
Proceedings of the ICPPW 2009, 2009

Building heterogeneous reconfigurable systems using threads.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Building heterogeneous reconfigurable systems with a hardware microkernel.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Achieving Programming Model Abstractions for Reconfigurable Computing.
IEEE Trans. Very Large Scale Integr. Syst., 2008

An Infrastructure for Hardware-Software Co-Design of Embedded Real-Time Java Applications.
Proceedings of the 11th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2008), 2008

Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Supporting High Level Language Semantics Within Hardware Resident Threads.
Proceedings of the FPL 2007, 2007

2006
Run-Time Services for Hybrid CPU/FPGA Systems on Chip.
Proceedings of the 27th IEEE Real-Time Systems Symposium (RTSS 2006), 2006

Hthreads: A Computational Model for Reconfigurable Devices.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Enabling a Uniform Programming Model Across the Software/Hardware Boundary.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transforms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004
Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link.
IEEE Micro, 2004

Programming Models for Hybrid CPU/FPGA Chips.
Computer, 2004

2003
Using the Multi-Threaded Computation Model as a Unifying Framework for Hardware-Software Co-Design and Implementation.
Proceedings of the 9th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS Fall 2003), 2003

Architectural Frameworks for MPP Systems on a Chip.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

SCIMPS: An Integrated Approach to Distributed Processing in Sensor Webs.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Interprocess communications in the AN/BSY-2 distributed computer system: a case study.
J. Syst. Softw., 2002

A Framework for Using Benefit Functions In Complex Real Time Systems.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

1998
Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum.
Proceedings of the 1998 workshop on Computer architecture education, 1998

1997
Seeking Solutions in Configurable Computing.
Computer, 1997

Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1995
Rapid prototype of a hardware emulator for a SIMD processor array.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Rapid prototype of an SIMD processor array (using FPGA's).
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

1991
PAWS: A Performance Evaluation Tool for Parallel Computing Systems.
Computer, 1991


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