Peter Lidén

According to our database1, Peter Lidén authored at least 11 papers between 1991 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

1996
A fault model for switch-level simulation of gate-to-drain shorts.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1995
Fault Simulation and Physical Fault Injection Applied to MOS Transistor Networks.
PhD thesis, 1995

Switch-level modeling of transistor-level stuck-at faults.
Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

A Switch-level Algorithm for Simulation of Transients in Combinational Logic.
Proceedings of the Digest of Papers: FTCS-25, 1995

1994
Using heavy-ion radiation to validate fault-handling mechanisms.
IEEE Micro, 1994

On Latching Probability of Particle Induced Transients in Combinational Networks.
Proceedings of the Digest of Papers: FTCS/24, 1994

Modeling of Intermediate Node States in switch-Level Networks.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Efficient modeling of switch-level networks containing undetermined logic node states.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Transistor Fault Coverage for Self-Testing CMOS Checkers.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991
Two Fault Injection Techniques for Test of Fault Handling Mechanisms.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991


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