Peter M. Maurer

According to our database, Peter M. Maurer authored at least 50 papers between 1983 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Generating Random XML Files Using DGL.

Peter M. Maurer, John Carbone

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022

Teaching Induction and Deductive Reasoning.

Peter M. Maurer

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2022

2021

Computer Science Theory from a Practical Point of View.

Peter M. Maurer

Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

Massive Generation of Data with Random Variates.

Peter M. Maurer

Proceedings of the Annual Modeling and Simulation Conference, 2021

2019

A nominal/inertial delay metamorphic differential simulator.

Peter M. Maurer

Proceedings of the 2019 Summer Simulation Conference, 2019

2017

Finite random variates using differential search trees.

Peter M. Maurer

Proceedings of the Summer Simulation Multi-Conference, 2017

2016

Time-parallel multi-delay logic simulation.

Peter M. Maurer

Proceedings of the Symposium on Theory of Modeling & Simulation, 2016

2015

A second look at oblivious simulation.

Peter M. Maurer

Proceedings of the Conference on Summer Computer Simulation, 2015

Levelized compiled code multi-delay logic simulation.

Peter M. Maurer

Proceedings of the Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium, 2015

2014

A universal symmetry detection algorithm.

Peter M. Maurer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Metamorphic differential simulation using the multi-delay timing model.

Peter M. Maurer

Proceedings of the 2013 Spring Simulation Multiconference, SpringSim '13, 2013

2012

Extending symmetric variable-pair transitivities using state-space transformations.

Peter M. Maurer

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Conjugate symmetry.

Peter M. Maurer

Formal Methods Syst. Des., 2011

2006

Using conjugate symmetries to enhance gate-level simulations.

Peter M. Maurer

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Converting command-line applications into binary components.

Peter M. Maurer

Softw. Pract. Exp., 2005

How to Make Program Assessment Work for You.

William B. Poucher, Peter M. Maurer

Proceedings of The 2005 International Conference on Frontiers in Education: Computer Science and Computer Engineering, 2005

2004

Metamorphic Programming: Unconventional High Performance.

Peter M. Maurer

Computer, 2004

2003

Efficient event-driven simulation by exploiting the output observability of gate clusters.

Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Random Characterization of Design Automation Algorithms.

Sandeep K. Kondapuram, Peter M. Maurer

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2001

Identifying an appropriate view of software components for undergraduate education.

Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide

Proceedings of the 32rd SIGCSE Technical Symposium on Computer Science Education, 2001

2000

Components: What If They Gave a Revolution and Nobody Came?

Peter M. Maurer

Computer, 2000

State-Machine Based Logic Simulation Using Three Logic Values.

Peter M. Maurer, William J. Schilp

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Event Driven Simulation Without Loops or Conditionals.

Peter M. Maurer

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Logic Simulation Using Networks of State Machines.

Peter M. Maurer

Proceedings of the 2000 Design, 2000

1999

Efficient Simulation for Hierarchical and Partitioned Circuits.

Peter M. Maurer

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Software Bit-Slicing: A Technique for Improving Simulation Performance.

Peter M. Maurer, William J. Schilp

Proceedings of the 1999 Design, 1999

1997

The inversion algorithm for digital simulation.

Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996

Bit-parallel multidelay simulation.

Yun Sik Lee, Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Is Compiled Simulation Really Faster than Interpreted Simulation?

Peter M. Maurer

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Unit delay simulation with the inversion algorithm.

William J. Schilp, Peter M. Maurer

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1994

Gateways: a technique for adding event-driven behavior to compiled simulations.

Peter M. Maurer, Yun Sik Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1993

The shadow algorithm: a scheduling technique for both compiled and interpreted simulation.

Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Parallel multi-delay simulation.

Yun Sik Lee, Peter M. Maurer

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Two new techniques for unit-delay compiled simulation.

Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

The Design and Implementation of a Grammar-based Data Generator.

Peter M. Maurer

Softw. Pract. Exp., 1992

Two New Techniques for Compiled Multi-Delay Logic Simulation.

Yun Sik Lee, Peter M. Maurer

Proceedings of the 29th Design Automation Conference, 1992

1991

Scheduling blocks of hierarchical compiled simulation of combinational circuits.

Peter M. Maurer

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990

Generating Test Data with Enhanced Context-Free Grammars.

Peter M. Maurer

IEEE Softw., 1990

Dynamic Functional Testing for VLSI Circuits.

Peter M. Maurer

IEEE Des. Test Comput., 1990

Optimization of the Parallel Technique for Compiled Unit-Delay Simulation.

Peter M. Maurer

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

LECSIM: A Levelized Event Driven Compiled Logic Simulation.

Zhicheng Wang, Peter M. Maurer

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Techniques for Unit-Delay Compiled Simulation.

Peter M. Maurer, Zhicheng Wang

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

The FHDL ROM tools.

Peter M. Maurer, Craig D. Morency

Proceedings of the 28th Annual Southeast Regional Conference, 1990

The FHDL PLA tools.

Peter M. Maurer, Craig D. Morency

Proceedings of the 28th Annual Southeast Regional Conference, 1990

The FHDL macro processor.

Peter M. Maurer

Proceedings of the 28th Annual Southeast Regional Conference, 1990

1989

Scheduling High-Level Blocks for Functional Simulation.

Zhicheng Wang, Peter M. Maurer

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A logic-to-logic comparator for VLSI layout verification.

Peter M. Maurer, Alexander D. Schapira

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Design verification of the WE 32106 math accelerator unit.

Peter M. Maurer

IEEE Des. Test, 1988

Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor.

Peter M. Maurer

Proceedings of the International Conference on Parallel Processing, 1988

1983

The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs.

Peter M. Maurer, Arthur E. Oldehoeft

Comput. Lang., 1983