Peter R. Cappello

According to our database1, Peter R. Cappello authored at least 47 papers between 1981 and 2018.

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Bibliography

2018
A Development and Deployment Framework for Distributed Branch-and-Bound.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics, 2018

2008
Application-specific Processor Architecture: Then and Now.
Signal Processing Systems, 2008

2007
A Development and Deployment Framework for Distributed Branch and Bound.
Proceedings of the Handbook of Approximation Algorithms and Metaheuristics., 2007

2006
Multicore processors as Array Processors: Research Opportunities.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Advanced eager scheduling for Java-based adaptive parallel computing.
Concurrency - Practice and Experience, 2005

JICOS: A Java-Centric Network Computing Service.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

2002
CX: A scalable, robust network for parallel computing.
Scientific Programming, 2002

Advanced eager scheduling for Java-based adaptively parallel computing.
Proceedings of the 2002 Joint ACM-ISCOPE Conference on Java Grande 2002, 2002

Automatic Processor Lower Bound Formulas for Array Computations.
Proceedings of the International Symposium on Parallel Architectures, 2002

2001
A scalable, robust network for parallel computing.
Proceedings of the ACM 2001 Java Grande Conference, Stanford University, California, USA, 2001

2000
Processor-time-optimal systolic arrays.
Parallel Algorithms Appl., 2000

Javelin++: scalability issues in global computing.
Concurrency - Practice and Experience, 2000

Internet-Based TSP Computation with Javelin++.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000

Javelin 2.0: Java-Based Parallel Computing on the Internet.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

1999
Javelin: Parallel computing on the internet.
Future Gener. Comput. Syst., 1999

1998
Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems.
Int. J. Found. Comput. Sci., 1998

1997
Javelin: Internet-based Parallel Computing using Java.
Concurrency - Practice and Experience, 1997

1996
A Processor-Time-Minimal Design for 3D Rectilinear Mesh Algorithms.
Parallel Processing Letters, 1996

1995
Converting affine recurrence equations to quasi-uniform recurrence equations.
VLSI Signal Processing, 1995

A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
A Period-Processor-Time-Minimal Schedule for Cubical Mesh Algorithms.
IEEE Trans. Parallel Distrib. Syst., 1994

Implementing the 3D Alternating Direction Method on the Hypercube.
J. Parallel Distributed Comput., 1994

Bounded Broadcast in Systolic Arrays.
International Journal of High Speed Computing, 1994

A processor-time-minimal schedule for the standard tensor product algorithm.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1993
Systolic Arrays for Integer Chinese Remaindering.
Parallel Comput., 1993

1992
A Processor-Time-Minimal Systolic Array for Transitive Closure.
IEEE Trans. Parallel Distrib. Syst., 1992

Correction to "A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms".
IEEE Trans. Parallel Distrib. Syst., 1992

A Processor-Time-Minimal Systolic Array for Cubical Mesh Algorithms.
IEEE Trans. Parallel Distrib. Syst., 1992

Systolic Super Summation with Reduced Hardware.
IEEE Trans. Computers, 1992

1991
Decomposing polynomial interpolation for systolic arrays.
Int. J. Comput. Math., 1991

A period-processor-time-minimal systolic array for cubical mesh algorithms.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

1990
Easily Testable Iterative Logic Arrays.
IEEE Trans. Computers, 1990

Systolic computation of interpolating polynomials.
Computing, 1990

1989
Scheduling a system of nonsingular affine recurrence equations onto a processor array.
VLSI Signal Processing, 1989

The SDEF Programming System.
J. Parallel Distributed Comput., 1989

1988
Application-specific CAD of VLSI second-order sections.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1988

Systolic architectures for vector quantization.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1988

Systolic Super Summation.
IEEE Trans. Computers, 1988

1987
Gaussian Elimination on a Hypercube Automaton.
J. Parallel Distributed Comput., 1987

The SDEF Systolic Programming System.
Proceedings of the International Conference on Parallel Processing, 1987

Application-Specific CAD of High-Throughout IIR Filters.
Proceedings of the COMPCON'87, 1987

1985
A Mesh Automaton for Solving Dense Linear Systems.
Proceedings of the International Conference on Parallel Processing, 1985

1984
A fast tally structure and applications to signal processing.
Proceedings of the IEEE International Conference on Acoustics, 1984

1983
A VLSI Layout for a Pipelined Dadda Multiplier
ACM Trans. Comput. Syst., 1983

Unifying VLSI Array Designs with Geometric Transformations.
Proceedings of the International Conference on Parallel Processing, 1983

Optimal choice of intermediate latching to maximize throughput in VLSI circuits.
Proceedings of the IEEE International Conference on Acoustics, 1983

1981
Some intractable problems in digital signal processing.
Proceedings of the IEEE International Conference on Acoustics, 1981


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