Cheng-Wen Wu

According to our database1, Cheng-Wen Wu authored at least 228 papers between 1987 and 2020.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2004, "For contributions to design and test of array structures.".

Timeline

Legend:

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Online presence:

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Bibliography

2020
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR, 2020

A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.
Proceedings of the IEEE International Test Conference in Asia, 2020

Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.
Proceedings of the IEEE European Test Symposium, 2020

A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
The Last Byte: Baseball and Testing.
IEEE Des. Test, 2019

Asian Test Symposium - Past, Present and Future -.
Proceedings of the IEEE International Test Conference, 2019

2018
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2018

RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction.
Proceedings of the IEEE International Test Conference in Asia, 2018

Symbiotic Controller Design Using a Memory-Based FSM Model.
Proceedings of the 27th IEEE International Symposium on Industrial Electronics, 2018

Covering hard-to-detect defects by thermal quorum sensing.
Proceedings of the 23rd IEEE European Test Symposium, 2018

A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories.
IEEE Trans. Computers, 2017

Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package.
IEEE Des. Test, 2017

Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache.
IEEE Des. Test, 2017

Can IOT make semiconductor great again?
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Highly reliable and low-cost symbiotic IOT devices and systems.
Proceedings of the IEEE International Test Conference, 2017

Symbiotic system models for efficient IGT system design and test.
Proceedings of the International Test Conference in Asia, 2017

Cell-aware test generation time reduction by using switch-level ATPG.
Proceedings of the International Test Conference in Asia, 2017

An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
A Local Parallel Search Approach for Memory Failure Pattern Identification.
IEEE Trans. Computers, 2016

Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.
IEEE Des. Test, 2016

Is IoT coming to the rescue of semiconductor?
Proceedings of the 21th IEEE European Test Symposium, 2016

A fast sweep-line-based failure pattern extractor for memory diagnosis.
Proceedings of the 21th IEEE European Test Symposium, 2016

Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015
YM500v2: a small RNA sequencing (smRNA-seq) database for human cancer miRNome research.
Nucleic Acids Res., 2015

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015

System-level test coverage prediction by structural stress test data mining.
Proceedings of the VLSI Design, Automation and Test, 2015

2014
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base.
IEEE Trans. Very Large Scale Integr. Syst., 2014

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test, 2014

Redundancy architectures for channel-based 3D DRAM yield improvement.
Proceedings of the 2014 International Test Conference, 2014

BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2013

AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Write Current Self-Configuration Scheme for MRAM Yield Improvement.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Low-Cost Error Tolerance Scheme for 3-D CMOS Imagers.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Generalization of an Enhanced ECC Methodology for Low Power PSRAM.
IEEE Trans. Computers, 2013

A hybrid ECC and redundancy technique for reducing refresh power of DRAMs.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Special session 4C: Hot topic 3D-IC design and test.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

3D-IC interconnect test, diagnosis, and repair.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

An FPGA-based test platform for analyzing data retention time distribution of DRAMs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Holistic approach to low-power system design.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

An enhanced double-TSV scheme for defect tolerance in 3D-IC.
Proceedings of the Design, Automation and Test in Europe, 2013

Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints.
Proceedings of the 22nd Asian Test Symposium, 2013

Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A Memory Failure Pattern Analyzer for memory diagnosis and repair.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Cost modeling and analysis for interposer-based three-dimensional IC.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

3D-IC BISR for stacked memories using cross-die spares.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

A built-in self-test scheme for 3D RAMs.
Proceedings of the 2012 IEEE International Test Conference, 2012

A memory yield improvement scheme combining built-in self-repair and error correction codes.
Proceedings of the 2012 IEEE International Test Conference, 2012

On test and repair of 3D random access memory.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A Memory Built-In Self-Repair Scheme Based on Configurable Spares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Special session: Hot topic design and test of 3D and emerging memories.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Training-based forming process for RRAM yield improvement.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A built-in self-test scheme for the post-bond test of TSVs in 3D ICs.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.
Proceedings of the 2011 IEEE International Test Conference, 2011

DfT Architecture for 3D-SICs with Multiple Towers.
Proceedings of the 16th European Test Symposium, 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A self-testing and calibration method for embedded successive approximation register ADC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
A Mesh-Structured Scalable IPsec Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Single- and Multi-core Configurable AES Architectures for Flexible Security.
IEEE Trans. Very Large Scale Integr. Syst., 2010

An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2010

SOC Test Architecture and Method for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Built-In Self-Repair Schemes for Flash Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Economic Analysis of the HOY Wireless Test Methodology.
IEEE Des. Test Comput., 2010

On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A low-cost and scalable test architecture for multi-core chips.
Proceedings of the 15th European Test Symposium, 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

An adaptive code rate EDAC scheme for random access memory.
Proceedings of the Design, Automation and Test in Europe, 2010

Fast identification of operating current for toggle MRAM by spiral search.
Proceedings of the 47th Design Automation Conference, 2010

An error tolerance scheme for 3D CMOS imagers.
Proceedings of the 47th Design Automation Conference, 2010

Performance Characterization of TSV in 3D IC via Sensitivity Analysis.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

A Test Integration Methodology for 3D Integrated Circuits.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

Is 3D integration an opportunity or just a hype?
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories.
IEEE Des. Test Comput., 2009

An Adaptive-Rate Error Correction Scheme for NAND Flash Memory.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Test Integration for SOC Supporting Very Low-Cost Testers.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Write Disturbance Modeling and Testing for MRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2008

A Systematic Approach to Memory Test Time Reduction.
IEEE Des. Test Comput., 2008

Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
STEAC: A Platform for Automatic SOC Test Integration.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.
IET Comput. Digit. Tech., 2007

Raisin: Redundancy Analysis Algorithm Simulation.
IEEE Des. Test Comput., 2007

Economic Aspects of Memory Built-in Self-Repair.
IEEE Des. Test Comput., 2007

SDRAM Delay Fault Modeling and Performance Testing.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

A prototype of a wireless-based test system.
Proceedings of the 2007 IEEE International SOC Conference, 2007

Diagnosis for MRAM write disturbance fault.
Proceedings of the 2007 IEEE International Test Conference, 2007

2006
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Session Abstract.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

A Built-In Self-Repair Scheme for NOR-Type Flash Memory.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Fault-Pattern Oriented Defect Diagnosis for Flash Memory.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006

Testing MRAM for Write Disturbance Fault.
Proceedings of the 2006 IEEE International Test Conference, 2006

An Enhanced EDAC Methodology for Low Power PSRAM.
Proceedings of the 2006 IEEE International Test Conference, 2006

A network security processor design based on an integrated SOC design and test platform.
Proceedings of the 43rd Design Automation Conference, 2006

2005
A built-in self-repair design for RAMs with 2-D redundancy.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Flash Memory Built-In Self-Diagnosis with Test Mode Control.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A BIST Scheme for FPGA Interconnect Delay Faults.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A systematic approach to reducing semiconductor memory test time in mass production.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

SOC Testing Methodology and Practice.
Proceedings of the 2005 Design, 2005

Flash Memory Die Sort by a Sample Classification Method.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Design and test of a scalable security processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

A configurable AES processor for enhanced security.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Graph-Based Approach to Power-Constrained SOC Test Scheduling.
J. Electron. Test., 2004

Efficient and Economical Test Equipment Setup Using Procorrelation.
IEEE Des. Test Comput., 2004

A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

MRAM Defect Analysis and Fault Modeli.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

An Application-Independent Delay Testing Methodology for Island-Style FPGA.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

Failure Factor Based Yield Enhancement for SRAM Designs.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

On Test and Diagnostics of Flash Memories.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Fail Pattern Identification for Memory Built-In Self-Repair.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

An HMAC processor with integrated SHA-1 and MD5 algorithms.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

SRAM delay fault modeling and test algorithm development.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Built-in redundancy analysis for memory yield improvement.
IEEE Trans. Reliab., 2003

Asymmetric High-Radix Signed-Digit Number Systems for Carry-Free Addition.
J. Inf. Sci. Eng., 2003

Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.
J. Inf. Sci. Eng., 2003

Testing and Diagnosis Methodologies for Embedded Content Addressable Memories.
J. Electron. Test., 2003

A high-throughput low-cost AES processor.
IEEE Commun. Mag., 2003

Test and Diagnosis of Word-Oriented Multiport Memories.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Fault Pattern Oriented Defect Diagnosis for Memories.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Combinational circuit fault diagnosis using logic emulation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

FAME: A Fault-Pattern Based Memory Failure Analysis Framework.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Processor-Based Built-In Self-Repair Design for Embedded Memories.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Defect Oriented Fault Analysis for SRAM.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Design of a scalable RSA and ECC crypto-processor.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

A highly efficient AES cipher chip.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Efficient FFT network testing and diagnosis schemes.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Fault simulation and test algorithm generation for random accessmemories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Hierarchical Test Methodology for Systems on Chip.
IEEE Micro, 2002

A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM.
J. Electron. Test., 2002

Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.
J. Electron. Test., 2002

Testing and Diagnosing Embedded Content Addressable Memories.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

Diagonal Test and Diagnostic Schemes for Flash Memorie.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Flash Memory Built-In Self-Test Using March-Like Algorithm.
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

A Hierarchical Test Scheme for System-On-Chip Designs.
Proceedings of the 2002 Design, 2002

Test Scheduling of BISTed Memory Cores for SOC.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

Test Scheduling and Test Access Architecture Optimization for System-on-Chip.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

On-chip Analog Response Extraction with 1-Bit ? - Modulators.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001
Unified VLSI systolic array design for LZ data compression.
IEEE Trans. Very Large Scale Integr. Syst., 2001

VLSI Design of RSA Cryptosystem Based on the Chinese Remainder Theorem.
J. Inf. Sci. Eng., 2001

Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

March-based RAM diagnosis algorithms for stuck-at and coupling faults.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Memory fault diagnosis by syndrome compression.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
Proceedings of the 38th Design Automation Conference, 2001

A Built-in Self-Test and Self-Diagnosis Scheme for Heterogeneous SRAM Clusters.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

RSA cryptosystem design based on the Chinese remainder theorem.
Proceedings of ASP-DAC 2001, 2001

Processor-programmable memory BIST for bus-connected embedded memories.
Proceedings of ASP-DAC 2001, 2001

2000
Testing and Diagnosing Dynamic Reconfigurable FPGA.
VLSI Design, 2000

Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Testing content-addressable memories using functional fault modelsand march-like algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A fast signature computation algorithm for LFSR and MISR.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A Low-Power CAM Design for LZ Data Compression.
IEEE Trans. Computers, 2000

A Probabilistic Model for Path Delay Fault Testing.
J. Inf. Sci. Eng., 2000

Simulation-Based Test Algorithm Generation for Random Access Memories.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

Built-in self-test and fault diagnosis for lookup table FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Error Catch and Analysis for Semiconductor Memories Using March Tests.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

BRAINS: A BIST Compiler for Embedded Memories.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Cost and Benefit Models for Logic and Memory BIST.
Proceedings of the 2000 Design, 2000

A built-in self-test and self-diagnosis scheme for embedded SRAM.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A Testable/Fault Tolerant FFT Processor Design.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A waveform simulator based on Boolean process.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

An FPGA-based re-configurable functional tester for memory chips.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A programmable built-in self-test core for embedded memories.
Proceedings of ASP-DAC 2000, 2000

Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem.
Proceedings of ASP-DAC 2000, 2000

1999
An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Low-Cost Modular Totally Self-Checking Checker Design for m-out-of-n Code.
IEEE Trans. Computers, 1999

Test Energy Minimization for C-Testable ILAs.
J. Inf. Sci. Eng., 1999

TSC Berger-Code Checker Design for 2r-1-Bit Information.
J. Inf. Sci. Eng., 1999

A Programmable BIST Core for Embedded DRAM.
IEEE Des. Test Comput., 1999

A novel approach to testing LUT-based FPGAs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

RAMSES: A Fast Memory Fault Simulator.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Testable and Fault Tolerant Design for FFT Networks.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Defect Level Prediction Using Multi-Model Fault Coverage.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Testing Interconnects of Dynamic Reconfigurable FPGAs.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Design of CMOS PSCD Circuits and Checkers for Stuck-At and Stuck-On Faults.
VLSI Design, 1998

Sequential circuit fault simulation using logic emulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Control and Observation Structures for Analog Circuits.
IEEE Des. Test Comput., 1998

A Probabilistic Model for Path Delay Faults.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Testing Embedded Memories: Is BIST the Ultimate Solution?
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

On-Line Error Detection Schemes for a Systolic Finite-Field Inverter.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy.
IEEE Trans. Computers, 1997

Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates?
J. Inf. Sci. Eng., 1997

Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications.
J. Circuits Syst. Comput., 1997

High-speed C-testable systolic array design for Galois-field inversion.
Proceedings of the European Design and Test Conference, 1997

On energy efficiency of VLSI testing.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Cell delay fault testing for iterative logic arrays.
J. Electron. Test., 1996

A MISR Computation Algorithm for Fast Signature Simulation.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995
Bit-level systolic arrays for finite-field multiplications.
J. VLSI Signal Process., 1995

C-testable design techniques for iterative logic arrays.
IEEE Trans. Very Large Scale Integr. Syst., 1995

Cellular automata for efficient parallel logic and fault simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

DC control and observation structures for analog circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.
IEEE Trans. Computers, 1994

General Modular Multiplication by Block Multiplication and Table Lookup.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Logic and Fault Simulation by Cellular Automata.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Fault-Tolerant FFT Butterfly Network Design.
J. Inf. Sci. Eng., 1993

1991
Bit-level pipelined 2-D digital filters for real-time image processing.
IEEE Trans. Circuits Syst. Video Technol., 1991

Easily Testable Cellular Array Multipliers.
J. Inf. Sci. Eng., 1991

Designing Self-Testable Cellular Arrays.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

1990
Easily Testable Iterative Logic Arrays.
IEEE Trans. Computers, 1990

Relating Tiling and Coloring to Testing of Combinational Iterative Logic Arrays.
J. Inf. Sci. Eng., 1990

1988
Application-specific CAD of VLSI second-order sections.
IEEE Trans. Acoust. Speech Signal Process., 1988

1987
Computer-aided design of VLSI second-order sections.
Proceedings of the IEEE International Conference on Acoustics, 1987

Application-Specific CAD of High-Throughout IIR Filters.
Proceedings of the COMPCON'87, 1987


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