Cheng-Wen Wu
Orcid: 0000-0001-8614-7908Affiliations:
- Southern Taiwan University of Science and Technology, Tainan, Taiwan
- National Tsing Hua University, Hsinchu, Taiwan (1988 - 2023)
According to our database1,
Cheng-Wen Wu
authored at least 251 papers
between 1987 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2004, "For contributions to design and test of array structures.".
Timeline
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Online presence:
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Bibliography
2023
A 40-nm 1.89-pJ/SOP Scalable Convolutional Spiking Neural Network Learning Core With On-Chip Spatiotemporal Back-Propagation.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
Effective and Efficient Testing of Large Numbers of Inter-Die Interconnects in Chiplet-Based Multi-Die Packages.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
Effective and Efficient Test and Diagnosis Pattern Generation for Many Inter-Die Interconnects in Chiplet-Based Packages.
Proceedings of the IEEE International 3D Systems Integration Conference, 2023
2022
Enhancing Fan Engagement in a 5G Stadium With AI-Based Technologies and Live Streaming.
IEEE Syst. J., 2022
Impact Position Estimation for Baseball Batting with a Force-Irrelevant Vibration Feature.
Sensors, 2022
A Thermal Quorum Sensing Scheme for Enhancement of Integrated-Circuit Reliability and Lifetime.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE International Test Conference, 2022
Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and Reliability.
Proceedings of the IEEE International Test Conference in Asia, 2022
Proceedings of the IEEE International Test Conference in Asia, 2022
Proceedings of the IEEE 31st Asian Test Symposium, 2022
Battery Pack Reliability and Endurance Enhancement for Electric Vehicles by Dynamic Reconfiguration.
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
IEEE Des. Test, 2021
An Improved STBP for Training High-Accuracy and Low-Spike-Count Spiking Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
A Power-Efficient Binary-Weight Spiking Neural Network Architecture for Real-Time Object Classification.
CoRR, 2020
A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices.
Proceedings of the IEEE International Test Conference in Asia, 2020
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.
Proceedings of the IEEE European Test Symposium, 2020
A 90nm 103.14 TOPS/W Binary-Weight Spiking Neural Network CMOS ASIC for Real-Time Object Classification.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2019
Proceedings of the IEEE International Test Conference, 2019
2018
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2018
RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction.
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 27th IEEE International Symposium on Industrial Electronics, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 27th IEEE Asian Test Symposium, 2018
A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
IEEE Trans. Computers, 2017
IEEE Des. Test, 2017
IEEE Des. Test, 2017
Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the International Test Conference in Asia, 2017
Proceedings of the International Test Conference in Asia, 2017
An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages.
Proceedings of the 26th IEEE Asian Test Symposium, 2017
2016
IEEE Trans. Computers, 2016
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement.
IEEE Des. Test, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
YM500v2: a small RNA sequencing (smRNA-seq) database for human cancer miRNome research.
Nucleic Acids Res., 2015
A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
2014
Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs.
IEEE Des. Test, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Computers, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints.
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
A memory yield improvement scheme combining built-in self-repair and error correction codes.
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base.
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 16th European Test Symposium, 2011
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011
Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
A self-testing and calibration method for embedded successive approximation register ADC.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
An Efficient Multimode Multiplier Supporting AES and Fundamental Operations of Public-Key Cryptosystems.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEEE Des. Test Comput., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Test and Diagnosis Algorithm Generation and Evaluation for MRAM Write Disturbance Fault.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques.
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
BIST-based diagnosis scheme for field programmable gate array interconnect delay faults.
IET Comput. Digit. Tech., 2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
CAMEL: An Efficient Fault Simulator with Coupling Fault Simulation Enhancement for CAMs.
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
A network security processor design based on an integrated SOC design and test platform.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
J. Electron. Test., 2004
IEEE Des. Test Comput., 2004
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Practical considerations in applying Σ-Δ modulation-based analog BIST to sampled-data systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
J. Inf. Sci. Eng., 2003
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults.
J. Inf. Sci. Eng., 2003
J. Electron. Test., 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
J. Electron. Test., 2002
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.
J. Electron. Test., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
J. Inf. Sci. Eng., 2001
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
IEEE Trans. Very Large Scale Integr. Syst., 2000
Testing content-addressable memories using functional fault modelsand march-like algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
Proceedings of ASP-DAC 2000, 2000
Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem.
Proceedings of ASP-DAC 2000, 2000
1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Computers, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
VLSI Design, 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
1997
IEEE Trans. Computers, 1997
Does There Exist a Combinational TSC Checker for 1/3 Code Using Only Primitive Gates?
J. Inf. Sci. Eng., 1997
Practical Realization of Multiple-Input Exclusive-OR Circuits for Low-Power Applications.
J. Circuits Syst. Comput., 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
1996
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module.
Proceedings of the 5th Asian Test Symposium (ATS '96), 1996
1995
J. VLSI Signal Process., 1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995
1994
Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.
IEEE Trans. Computers, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1993
1991
IEEE Trans. Circuits Syst. Video Technol., 1991
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
J. Inf. Sci. Eng., 1990
1988
IEEE Trans. Acoust. Speech Signal Process., 1988
1987
Proceedings of the IEEE International Conference on Acoustics, 1987
Application-Specific CAD of High-Throughout IIR Filters.
Proceedings of the COMPCON'87, 1987