Philippe Hurat

According to our database, Philippe Hurat authored at least 9 papers between 1989 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Predictive models and CAD methodology for pattern dependent variability.

Nishath Verghese, Richard Rouse, Philippe Hurat

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability.

Darsun Tsiena, Chien Kuo Wang, William W. J. Wang, Yajun Ran, Philippe Hurat, Nishath Verghese

Proceedings of the 2007 IEEE International SOC Conference, 2007

Addressing Parametric Impact of Systematic Pattern Variations in Digital IC Design.

Pei-Hua Wang, Brian Lee, Gus Han, Richard Rouse, Philippe Hurat, Nishath Verghese

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Modeling and Validation of Silicon Contour-Based Extraction and Simulation of Non-Uniform Devices.

Thierry Devoivre, Richard Rouse, Nishath Verghese, Philippe Hurat

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

DFM: Linking Design and Manufacturing.

Srinivas Raghvendra, Philippe Hurat

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Standard Cell Printability Grading and Hot Spot Detection.

Michel Côté, Philippe Hurat

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

2004

Layout Printability Optimization Using a Silicon Simulation Methodology.

Michel Côté, Philippe Hurat

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2001

A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow.

Michael Sanie, Michel Côté, Philippe Hurat, Vinod Malhotra

Proceedings of the 38th Design Automation Conference, 2001

1989

APLYSIE : un circuit neuro-mimétique : réalisation et intégration sur tranche. (APLYSIE: a neuro-mimetic integrated circuit. Design and wafer scale integration).

Philippe Hurat

PhD thesis, 1989