Yajun Ran

According to our database1, Yajun Ran authored at least 12 papers between 2003 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2007
Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability.
Proceedings of the 2007 IEEE International SOC Conference, 2007

2006
Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Designing via-configurable logic blocks for regular fabric.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
General skew constrained clock network sizing based on sequential linear programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Eliminating false positives in crosstalk noise analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004
The Magic of a Via-Configurable Regular Fabric.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

An integrated design flow for a via-configurable gate array.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Eliminating False Positives in Crosstalk Noise Analysis.
Proceedings of the 2004 Design, 2004

On designing via-configurable cell blocks for regular fabrics.
Proceedings of the 41th Design Automation Conference, 2004

Designing a via-configurable regular fabric.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Crosstalk noise in FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

Temporofunctional crosstalk noise analysis.
Proceedings of the 40th Design Automation Conference, 2003


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