Pietro Buccella

Affiliations:

École Polytechnique Fédérale de Lausanne, Switzerland

According to our database¹, Pietro Buccella authored at least 13 papers between 2014 and 2018.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2018

Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017

Substrate-currents-aware characterization of an integrated buck DC/DC converter for floor-plan optimization.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Toward low-power PPG-based heart rate monitoring using a MOS-PN hybrid photosensor.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

SPICE modeling of light induced current in silicon with 'Generalized' lumped devices.

[BibT_eX]

[DOI]

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Active guard ring characterization for Smart Power ICs.

[BibT_eX]

[DOI]

Proceedings of the 2016 MIXDES, 2016

Analysis of substrate currents propagation in HVCMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

Modeling parasitic vertical PNP in HVCMOS.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Spice simulation of passive protection in smart power ICs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Substrate noise modeling with dedicated CAD framework for smart power ICs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Modeling avalanche breakdown for ESD diodes in integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Optimization strategy of numerical simulations applied to EPFL substrate model.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Spice simulation of substrate minority carriers propagation with equivalent electrical circuit.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Pietro Buccella

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