Po-Yen Chiu

According to our database, Po-Yen Chiu authored at least 5 papers between 2007 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit.

Po-Yen Chiu, Ming-Dou Ker

Microelectron. Reliab., 2014

2013

Design of 2 × V_DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × V_DD Thin-Oxide Devices.

Ming-Dou Ker, Po-Yen Chiu

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.

Po-Yen Chiu, Ming-Dou Ker

Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2009

On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.

Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.

Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng

Proceedings of the 2007 IEEE International SOC Conference, 2007