Po-Yen Chiu

According to our database1, Po-Yen Chiu authored at least 5 papers between 2007 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2014
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit.
Microelectron. Reliab., 2014

2013
Design of 2 × VDD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 × VDD Thin-Oxide Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013

2009
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2007
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.
Proceedings of the 2007 IEEE International SOC Conference, 2007


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