Polen Kission

According to our database1, Polen Kission authored at least 9 papers between 1993 and 2000.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2000
The application of high-level synthesis techniques for the generation of pipelined reprogrammable microcontrollers.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1998
Architectural Simulation in the Context of Behavioral Synthesis.
Proceedings of the 1998 Design, 1998

1997
Embedded architectural simulation within behavioral synthesis environment.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Analysis of different protocol description styles in VHDL for high-level synthesis.
Proceedings of the conference on European design automation, 1996

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis.
Proceedings of the 33st Conference on Design Automation, 1996

1995
VHDL based design methodology for hierarchy and component re-use.
Proceedings of the Proceedings EURO-DAC'95, 1995

1994
Accelerating the design process by using architectural synthesis.
Proceedings of IEEE 5th International Workshop on Rapid System Prototyping, 1994

Structured Design Methodology for High-Level Design.
Proceedings of the 31st Conference on Design Automation, 1994

1993
Industrial experimentation of high-level synthesis.
Proceedings of the European Design Automation Conference 1993, 1993


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