Prashanth H. C.

Orcid: 0000-0002-9650-3731

According to our database1, Prashanth H. C. authored at least 20 papers between 2022 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Correction: Trainable windows for SincNet architecture.
EURASIP J. Audio Speech Music. Process., December, 2023

Trainable windows for SincNet architecture.
EURASIP J. Audio Speech Music. Process., December, 2023

Design and Evaluation of Inexact Computation based Systolic Array for Convolution.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

Design-Space Exploration of Multiplier Approximation in CNNs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

CellFlow: Automated Standard Cell Design Flow.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Error Diluted Approximate Multipliers Using Positive And Negative Compressors.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

SQRTLIB : Library of Hardware Square Root Designs.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Meta-Heuristic Optimization of Transistor Sizing in CMOS Digital Designs.
Proceedings of the 15th International Joint Conference on Computational Intelligence, 2023

ApproxCNN: Evaluation Of CNN With Approximated Layers Using In-Exact Multipliers.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023

EBASA: Error Balanced Approximate Systolic Array Architecture Design.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

IMAC: : A Pre-Multiplier And Integrated Reduction Based Multiply-And-Accumulate Unit.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

GCells: A Graph-Search Approach to Design Custom Cells for Computational Subsystems.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

2022
Design and Evaluation of Performance-efficient SoC-on-FPGA for Cloud-based Healthcare Applications.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022

Improving Digital Circuit Synthesis of Complex Functions using Binary Weighted Fitness and Variable Mutation Rate in Cartesian Genetic Programming.
Proceedings of the 14th International Joint Conference on Computational Intelligence, 2022

SOMALib: Library of Exact and Approximate Activation Functions for Hardware-efficient Neural Network Accelerators.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Design and Evaluation of In-Exact Compressor based Approximate Multipliers.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Evolutionary Standard Cell Synthesis of Unconventional Designs.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022


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