Preetisudha Meher

According to our database, Preetisudha Meher authored at least 11 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A Low Noise Low Power Neural Amplifier with Modified Folded-Cascode OTA to Detect Local Field Potential.

Nabanita Das, Sourav Nath, Koushik Guha, Preetisudha Meher, Krishna Lal Baishnab

Proceedings of the 2025 IEEE 19th International Conference on Industrial and Information Systems (ICIIS), 2025

Hardware Implementation of an Efficient Two Error Correcting BCH Code Decoder.

Maitreyee Das, Sourav Nath, Koushik Guha, Preetisudha Meher, Krishna Lal Baishnab

Proceedings of the 2025 IEEE 19th International Conference on Industrial and Information Systems (ICIIS), 2025

2024

An efficient hybrid multifactor mutual authentication and session key agreement scheme for patient monitoring system using IoMT.

Shanvendra Rai, Rituparna Paul, Subhasish Banerjee, Preetisudha Meher

Multim. Tools Appl., November, 2024

An anonymous mutual authentication and key agreement scheme in WMSN using physiological data.

Shanvendra Rai, Rituparna Paul, Subhasish Banerjee, Preetisudha Meher

Wirel. Networks, May, 2024

A Combined Approach of PUF and Physiological Data for Mutual Authentication and Key Agreement in WMSN.

Shanvendra Rai, Rituparna Paul, Subhasish Banerjee, Preetisudha Meher, Gulab Sah

J. Grid Comput., March, 2024

A Robust Smart Card based Authentication and Key Agreement Scheme for WSN using Fuzzy Extractor.

Rituparna Paul, Shanvendra Rai, Subhasish Banerjee, Preetisudha Meher

Peer Peer Netw. Appl., January, 2024

Codon usage in conserved sites is more biased compared to variable sites in the SARS-CoV-2 genome.

Madhusmita Dash, Annushree Kurmi, Preetisudha Meher, Siddhartha Sankar Satapathy, Nima D. Namsa

Int. J. Bioinform. Res. Appl., 2024

2020

An improved charge-sharing elimination pseudo-domino logic.

Sapna Rani Ghimiray, Preetisudha Meher, Pranab Kishore Dutta

Int. J. Circuit Theory Appl., 2020

2019

Design and Analysis of Dual Modulus Prescaler Circuit for Frequency Synthesizer.

Suraj Kumar Saw, Madhusudan Maiti, Preetisudha Meher

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

Ultralow power, noise immune stacked-double stage clocked-inverter domino technique for ultradeep submicron technology.

Sapna Rani Ghimiray, Preetisudha Meher, Pranab Kishore Dutta

Int. J. Circuit Theory Appl., 2018

2016

High-performance noise tolerant comparator design for arithmetic circuits.

Preetisudha Meher, Kamala Kanta Mahapatra

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016