Puneet Sareen

According to our database, Puneet Sareen authored at least 6 papers between 2010 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS.

Jens Anders, Sebastian Bader, Markus Dietl, Puneet Sareen, G. Rombach, Sotirios Tambouris, Maurits Ortmanns

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2015

A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter.

S. Fahmy, Markus Dietl, Puneet Sareen, Maurits Ortmanns, Jens Anders

Proceedings of the Nordic Circuits and Systems Conference, 2015

2012

A 2.5 GHz self-compensated, bandwidth tracking PLL with 0.8 ps jitter.

Mitesh Yogesh, Puneet Sareen, Markus Dietl, Ketan Dewan

Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

2011

Very high bandwidth semi-digital PLL with large operating frequency range.

Vivek Elangovan, Markus Dietl, Puneet Sareen

Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

A new low power and area efficient semi-digital PLL architecture for low bandwidth applications.

Markus Dietl, Puneet Sareen

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance.

Markus Dietl, Puneet Sareen

Proceedings of the 1st IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2010