Puneet Sareen
According to our database1,
Puneet Sareen
authored at least 6 papers
between 2010 and 2017.
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Bibliography
2017
A -245 dB FOM 48 fs rms jitter semi-digital PLL with intrinsic temperature compensation in 130 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A BW-tracking semi-digital PLL with near-optimal VCO phase noise shaping in low-cost 0.4 µm CMOS achieving 700 fs rms phase jitter.
Proceedings of the Nordic Circuits and Systems Conference, 2015
2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
A new low power and area efficient semi-digital PLL architecture for low bandwidth applications.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Low power, small die-size PLL using semi-digital storage instead of big loop filter capacitance.
Proceedings of the 1st IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2010