Qian Ge

According to our database, Qian Ge authored at least 9 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection.

Qian Ge

PhD thesis, 2019

Time Protection: The Missing OS Abstraction.

Qian Ge, Yuval Yarom, Tom Chothia, Gernot Heiser

Proceedings of the Fourteenth EuroSys Conference 2019, Dresden, Germany, March 25-28, 2019, 2019

2018

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware.

Qian Ge, Yuval Yarom, David A. Cock, Gernot Heiser

J. Cryptogr. Eng., 2018

No Security Without Time Protection: We Need a New Hardware-Software Contract.

Qian Ge, Yuval Yarom, Gernot Heiser

Proceedings of the 9th Asia-Pacific Workshop on Systems, 2018

2016

Do Hardware Cache Flushing Operations Actually Meet Our Expectations?

Qian Ge, Yuval Yarom, Gernot Heiser

CoRR, 2016

CATalyst: Defeating last-level cache side channel attacks in cloud computing.

Fangfei Liu, Qian Ge, Yuval Yarom, Frank McKeen, Carlos V. Rozas, Gernot Heiser, Ruby B. Lee

Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015

Mapping the Intel Last-Level Cache.

Yuval Yarom, Qian Ge, Fangfei Liu, Ruby B. Lee, Gernot Heiser

IACR Cryptol. ePrint Arch., 2015

Last-Level Cache Side-Channel Attacks are Practical.

Fangfei Liu, Yuval Yarom, Qian Ge, Gernot Heiser, Ruby B. Lee

Proceedings of the 2015 IEEE Symposium on Security and Privacy, 2015

2014

The Last Mile: An Empirical Study of Timing Channels on seL4.

David A. Cock, Qian Ge, Toby C. Murray, Gernot Heiser

Proceedings of the 2014 ACM SIGSAC Conference on Computer and Communications Security, 2014