Qianming Yang

According to our database, Qianming Yang authored at least 21 papers between 2007 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI.

Hongbing Tan, Libo Huang, Zhong Zheng, Hui Guo, Qianming Yang, Li Shen, Gang Chen, Liquan Xiao, Nong Xiao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024

2023

Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning.

Jing Zhang, Libo Huang, Hongbing Tan, Ling Yang, Zhong Zheng, Qianming Yang

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

2022

Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications.

Hongbing Tan, Run Yan, Ling Yang, Libo Huang, Liquan Xiao, Qianming Yang

Proceedings of the Algorithms and Architectures for Parallel Processing, 2022

2020

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors.

Zhuang Cao, Huayou Su, Qianming Yang, Junzhong Shen, Mei Wen, Chunyuan Zhang

IEEE Access, 2020

2019

Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA.

Zhuang Cao, Huayou Su, Qianming Yang, Mei Wen, Chunyuan Zhang

Proceedings of the IEEE INFOCOM 2019, 2019

2017

FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency.

Yuran Qiao, Junzhong Shen, Tao Xiao, Qianming Yang, Mei Wen, Chunyuan Zhang

Concurr. Comput. Pract. Exp., 2017

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA.

Yuran Qiao, Junzhong Shen, Dafei Huang, Qianming Yang, Mei Wen, Chunyuan Zhang

Proceedings of the Network and Parallel Computing, 2017

2015

Enabling a Uniform OpenCL Device View for Heterogeneous Platforms.

Dafei Huang, Changqing Xun, Nan Wu, Mei Wen, Chunyuan Zhang, Xing Cai, Qianming Yang

IEICE Trans. Inf. Syst., 2015

Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.

Tao Xiao, Yuran Qiao, Junzhong Shen, Qianming Yang, Mei Wen

Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2013

Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration.

Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang

J. Supercomput., 2013

SIR: A Secure Identifier-Based Inter-Domain Routing for Identifier/Locator Split Network.

Yaping Liu, Zhihong Liu, Baosheng Wang, Qianming Yang

IEICE Trans. Commun., 2013

Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing.

Jun Chai, Mei Wen, Nan Wu, Dafei Huang, Jing Yang, Xing Cai, Chunyuan Zhang, Qianming Yang

IEICE Trans. Inf. Syst., 2013

2012

Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression.

Yi He, Maolin Guan, Chunyuan Zhang, Tian Tian, Qianming Yang

Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012

The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only).

Mei Wen, Nan Wu, Qianming Yang, Chunyuan Zhang, Liang Zhao

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

2011

Tiled Multi-Core Stream Architecture.

Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang

Trans. High Perform. Embed. Archit. Compil., 2011

2010

Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels.

Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

SAT: A Stream Architecture Template for Embedded Applications.

Qianming Yang, Nan Wu, Mei Wen, Yi He, Huayou Su, Chunyuan Zhang

Proceedings of the 10th IEEE International Conference on Computer and Information Technology, 2010

2008

On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator.

Mei Wen, Nan Wu, Chunyuan Zhang, Qianming Yang, Ju Ren, Yi He, Wei Wu, Jun Chai, Maolin Guan, Changqing Xun

IEEE Micro, 2008

FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture.

Yi He, Ju Ren, Qianming Yang, Mei Wen, Nan Wu, Chunyuan Zhang

Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007

FT64: Scientific Computing with Streams.

Mei Wen, Nan Wu, Chunyuan Zhang, Wei Wu, Qianming Yang, Changqing Xun

Proceedings of the High Performance Computing, 2007

A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision.

Nan Wu, Qianming Yang, Mei Wen, Yi He, Changqing Xun, Chunyuan Zhang

Proceedings of the Advances in Computer Systems Architecture, 2007