Qingchuan Shi

According to our database, Qingchuan Shi authored at least 12 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2018

Declarative Resilience: A Holistic Soft-Error Resilient Multicore Architecture that Trades off Program Accuracy for Efficiency.

Hamza Omar, Qingchuan Shi, Masab Ahmad, Halit Dogan, Omer Khan

ACM Trans. Embed. Comput. Syst., 2018

CSSMT: Compiler Based Software Simultaneous Multithreading (SMT).

Yuanfang Chen, Qingchuan Shi, Xiaoming Li

Proceedings of the 26th Euromicro International Conference on Parallel, 2018

2017

Exploiting the Tradeoff between Program Accuracy and Soft-error Resiliency Overhead for Machine Learning Workloads.

Qingchuan Shi, Hamza Omar, Omer Khan

CoRR, 2017

2016

Locality-aware data replication in the last-level cache for large scale multicores.

Farrukh Hijaz, Qingchuan Shi, George Kurian, Srinivas Devadas, Omer Khan

J. Supercomput., 2016

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.

Qingchuan Shi, George Kurian, Farrukh Hijaz, Srinivas Devadas, Omer Khan

ACM Trans. Archit. Code Optim., 2016

2015

A Cross-Layer Multicore Architecture to Tradeoff Program Accuracy and Resilience Overheads.

Qingchuan Shi, Henry Hoffmann, Omer Khan

IEEE Comput. Archit. Lett., 2015

CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.

Masab Ahmad, Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.

George Kurian, Qingchuan Shi, Srinivas Devadas, Omer Khan

Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2013

Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.

Qingchuan Shi, Omer Khan

Computer, 2013

Towards efficient dynamic data placement in NoC-based multicores.

Qingchuan Shi, Farrukh Hijaz, Omer Khan

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages.

Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores.

Farrukh Hijaz, Qingchuan Shi, Omer Khan

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012