Farrukh Hijaz

Orcid: 0000-0001-9767-2847

According to our database1, Farrukh Hijaz authored at least 14 papers between 2011 and 2022.

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Bibliography

2022
Alternating Blind Identification of Power Sources for Mobile SoCs.
Proceedings of the ICPE '22: ACM/SPEC International Conference on Performance Engineering, Bejing, China, April 9, 2022

ARBench: Augmented Reality Benchmark For Mobile Devices.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2017
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
Locality-aware data replication in the last-level cache for large scale multicores.
J. Supercomput., 2016

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.
ACM Trans. Archit. Code Optim., 2016

2015
M-MAP: Multi-Factor Memory Authentication for Secure Embedded Processors.
IACR Cryptol. ePrint Arch., 2015

Efficient parallel packet processing using a shared memory many-core processor with hardware support to accelerate communication.
Proceedings of the 10th IEEE International Conference on Networking, 2015

Exploring the performance implications of memory safety primitives in many-core processors executing multi-threaded workloads.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

CRONO: A Benchmark Suite for Multithreaded Graph Algorithms Executing on Futuristic Multicores.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

2014
NUCA-L1: A Non-Uniform Access Latency Level-1 Cache Architecture for Multicores Operating at Near-Threshold Voltages.
ACM Trans. Archit. Code Optim., 2014

2013
Towards efficient dynamic data placement in NoC-based multicores.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltages.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
Low-Latency Mechanisms for Near-Threshold Operation of Private Caches in Shared Memory Multicores.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011
ARCc: A case for an architecturally redundant cache-coherence architecture for large multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011


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