R. Manikantan

Nagendra Dwarakanath Gulur

Raman Manikantan

Ramaswamy Govindarajan

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth.

[BibT_eX]

[DOI]

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

2012

Probabilistic Shared Cache Management (PriSM).

[BibT_eX]

[DOI]

Nagendra Dwarakanath Gulur

Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Supercomputing, 2012

2011

Performance Oriented Prefetching Enhancements Using Commit Stalls.

[BibT_eX]

[DOI]

J. Instr. Level Parallelism, 2011

NUcache: An efficient multicore cache organization based on Next-Use distance.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Extended histories: improving regularity and performance in correlation prefetchers.

[BibT_eX]

[DOI]

Nagendra Dwarakanath Gulur

Proceedings of the High Performance Embedded Architectures and Compilers, 2011

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

NUcache: a multicore cache organization based on next-use distance.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2008

Focused prefetching: performance oriented prefetching based on commit stalls.

[BibT_eX]

[DOI]