Mahesh Mehendale

According to our database, Mahesh Mehendale authored at least 56 papers between 1989 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge.

Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur

CoRR, 2023

A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces.

Adithya Krishna, Vignesh Ramanathan, Satyapreet Singh Yadav, Sahil Shah, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

Live Demonstration: Audio Inference using Neuromorphic Cochlea on RAMAN Accelerator.

Adithya Krishna, Hitesh Pavan Oleti, Anand Chauhan, H. Shankaranarayanan, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

2022

An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications.

Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications.

Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020

DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks.

Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag

Proceedings of the Computer Vision - ECCV 2020, 2020

2018

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.

R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2017

Session 14 overview: Deep-learning processors.

Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016

MicroRefresh: Minimizing Refresh Overhead in DRAM Caches.

Nagendra Gulur, R. Govindarajan, Mahesh Mehendale

Proceedings of the Second International Symposium on Memory Systems, 2016

Session 4 overview: Digital processors.

Mahesh Mehendale, Luke Shin

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

F1: Designing secure systems: Manufacturing, circuits and architectures.

Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015

A Comprehensive Analytical Performance Model of DRAM Caches.

Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan

Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering, Austin, TX, USA, January 31, 2015

8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process.

Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Accelerating H.264/HEVC video slice processing using application specific instruction set processor.

Dipan Kumar Mandal, Mihir Mody, Mahesh Mehendale, Naresh Yadav, Ghone Chaitanya, Piyali Goswami, Hetul Sanghvi, Niraj Nandan

Proceedings of the IEEE International Conference on Consumer Electronics, 2015

2014

ANATOMY: an analytical model of memory system performance.

Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth.

Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

A 28nm programmable and low power ultra-HD video codec engine.

Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A monolithic programmable Ultra-HD video codec engine.

Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry

Proceedings of the IEEE International Conference on Acoustics, 2014

2012

A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC.

Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities.

Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan

Proceedings of the International Conference on Supercomputing, 2012

2011

Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding.

Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi

IEEE Trans. Circuits Syst. Video Technol., 2011

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.

Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2006

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.

Subash Chandar G., Mahesh Mehendale, R. Govindarajan

J. VLSI Signal Process., 2006

SoC - The Road Ahead.

Mahesh Mehendale

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Challenges in the Design of Embedded Real-time DSP SoCs.

Mahesh Mehendale

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Multivoltage scheduling with voltage-partitioned variable storage.

Amitabh Menon, S. K. Nandy, Mahesh Mehendale

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Emerging markets: design goes global.

Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei

Proceedings of the 40th Design Automation Conference, 2003

2001

Functional Verification of Programmable DSP Cores.

Mahesh Mehendale, Santhosh Kumar Amanna

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Performance Considerations in Embedded DSP based System-On-a-Chip Designs.

Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

High Level Synthesis Of Multi-Precision Data Flow Graphs.

Vikas Agrawal, Anand Pande, Mahesh Mehendale

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Power Reduction Techniques for Portable DSP Applications.

Mahesh Mehendale, Sunil D. Sherlekar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Low Power Realization of Residue Number System Based FIR Filters.

M. N. Mahesh, Mahesh Mehendale

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999

Low Power Code Generation of Multiplication-free Linear Transforms.

Mahesh Mehendale, Sunil D. Sherlekar

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms.

M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Improving performance of high precision signal processing algorithms on programmable DSPs.

M. N. Mahesh, Mahesh Mehendale

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Integrated IC design approach based on software engineering paradigm.

Sunsil Sinha, Mahesh Mehendale

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Low-power realization of FIR filters on programmable DSPs.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

IEEE Trans. Very Large Scale Integr. Syst., 1998

mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic.

Amit Sinha, Mahesh Mehendale

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Extensions to Programmable DSP architectures for Reduced Power Dissipation.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.

Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Low Power Realization of FIR Filters Implemented using Distributed Arithmetic.

Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar

Proceedings of the ASP-DAC '98, 1998

1997

Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

Low power realization of FIR filters using multirate architectures.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Optimized Code Generation of Multiplication-free Linear Transforms.

Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar

Proceedings of the 33st Conference on Design Automation, 1996

1995

AATMA: an algorithm for technology mapping for antifuse-based FPGAs.

Mahesh Mehendale, M. K. Ram Prasad

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Synthesis of multiplier-less FIR filters with minimum number of additions.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Techniques for low power realization for FIR filters.

Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis.

Mahesh Mehendale, Biswadip Mitra

Proceedings of the Seventh International Conference on VLSI Design, 1994

Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures.

Mahesh Mehendale

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures.

Mahesh Mehendale, Kaushik Roy

Proceedings of the Sixth International Conference on VLSI Design, 1993

MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs.

Mahesh Mehendale

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

A System for Behavior Extraction from FPGA Implementations of Synchronous Designs.

Mahesh Mehendale

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

SLIM: A System for ASIC Library Management.

Mahesh Mehendale, P. Murugavel, M. Poornima

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

An approach to design flow management in CAD frameworks.

Mahesh Mehendale

Proceedings of the conference on European design automation, 1991

1989

FDT-a design tool for switched capacitor filters.

Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989