Nagendra Dwarakanath Gulur

According to our database, Nagendra Dwarakanath Gulur authored at least 15 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING.

Shashank Adavally, Alex Weaver, Pranathi Vasireddy, Krishna Kavi, Gayatri Mehta, Nagendra Gulur

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

2020

CHASM: Security Evaluation of Cache Mapping Schemes.

Fernando Mosquera, Nagendra Gulur, Krishna Kavi, Gayatri Mehta, Hua Sun

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

ExPress: Simultaneously Achieving Storage, Execution and Energy Efficiencies in Moderately Sparse Matrix Computations.

Shashank Adavally, Nagendra Gulur, Krishna Kavi, Alex Weaver, Pranoy Dutta, Benjamin Wang

Proceedings of the MEMSYS 2020: The International Symposium on Memory Systems, 2020

ATTC (@C): Addressable-TLB based Translation Coherence.

Harsh Gugale, Nagendra Gulur, Yashwant Marathe, Lizy K. John

Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2017

RLWS: A Reinforcement Learning based GPU Warp Scheduler.

Jayvant Anantpur, Nagendra Dwarakanath Gulur, Shivaram Kalyanakrishnan, Shalabh Bhatnagar, R. Govindarajan

CoRR, 2017

CSALT: context switch aware large TLB.

Yashwant Marathe, Nagendra Gulur, Jee Ho Ryoo, Shuang Song, Lizy K. John

Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB.

Jee Ho Ryoo, Nagendra Gulur, Shuang Song, Lizy K. John

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016

MicroRefresh: Minimizing Refresh Overhead in DRAM Caches.

Nagendra Gulur, R. Govindarajan, Mahesh Mehendale

Proceedings of the Second International Symposium on Memory Systems, 2016

2015

A Comprehensive Analytical Performance Model of DRAM Caches.

Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan

Proceedings of the 6th ACM/SPEC International Conference on Performance Engineering, Austin, TX, USA, January 31, 2015

Understanding the Performance Benefit of Asynchronous Data Transfers in OpenCL Programs Executing on Media Processors.

Nagendra Gulur, Narayanan L. Suriya

Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

2014

ANATOMY: an analytical model of memory system performance.

Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth.

Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets.

Vasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar

Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

2012

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities.

Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan

Proceedings of the International Conference on Supercomputing, 2012

2011

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.

Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011