Rachmad Vidya Wicaksana Putra

Orcid: 0000-0001-8597-4530

According to our database1, Rachmad Vidya Wicaksana Putra authored at least 31 papers between 2011 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
SpikeNAS: A Fast Memory-Aware Neural Architecture Search Framework for Spiking Neural Network Systems.
CoRR, 2024

2023
RescueSNN: Enabling Reliable Executions on Spiking Neural Network Accelerators under Permanent Faults.
CoRR, 2023

EnforceSNN: Enabling Resilient and Energy-Efficient Spiking Neural Network Inference considering Approximate DRAMs for Embedded Systems.
CoRR, 2023

TopSpark: A Timestep Optimization Methodology for Energy-Efficient Spiking Neural Networks on Autonomous Mobile Agents.
IROS, 2023

Mantis: Enabling Energy-Efficient Autonomous Mobile Agents with Spiking Neural Networks.
Proceedings of the 9th International Conference on Automation, Robotics and Applications, 2023

2022
tinySNN: Towards Memory- and Energy-Efficient Spiking Neural Networks.
CoRR, 2022

lpSpikeCon: Enabling Low-Precision Spiking Neural Network Processing for Efficient Unsupervised Continual Learning on Autonomous Agents.
Proceedings of the International Joint Conference on Neural Networks, 2022

SoftSNN: low-cost fault tolerance for spiking neural network accelerators under soft errors.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2021

Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework.
CoRR, 2021

Q-SpiNN: A Framework for Quantizing Spiking Neural Networks.
Proceedings of the International Joint Conference on Neural Networks, 2021

ReSpawn: Energy-Efficient Fault-Tolerance for Spiking Neural Networks considering Unreliable Memories.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Towards Energy-Efficient and Secure Edge AI: A Cross-Layer Framework ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

SparkXD: A Framework for Resilient and Energy-Efficient Spiking Neural Network Inference using Approximate DRAM.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

SpikeDyn: A Framework for Energy-Efficient Spiking Neural Networks with Continual and Unsupervised Learning Capabilities in Dynamic Environments.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
FSpiNN: An Optimization Framework for Memory-Efficient and Energy-Efficient Spiking Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

FSpiNN: An Optimization Framework for Memory- and Energy-Efficient Spiking Neural Networks.
CoRR, 2020

APNAS: Accuracy-and-Performance-Aware Neural Architecture Search for Neural Hardware Accelerators.
IEEE Access, 2020

DRMap: A Generic DRAM Data Mapping Policy for Energy-Efficient Processing of Convolutional Neural Networks.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
ROMANet: Fine-Grained Reuse-Driven Data Organization and Off-Chip Memory Access Management for Deep Neural Network Accelerators.
CoRR, 2019

2018
MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks.
CoRR, 2018

Robust Machine Learning Systems: Reliability and Security for Deep Neural Networks.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

HW/SW co-design and co-optimizations for deep learning.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2016
Kurtosis and energy based spectrum detection for SDR based RF monitoring system.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

An architecture design of SAD based template matching for fast queue counter in FPGA.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Parallel morphological template matching design for efficient human detection application.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016

Analog filters design in VLC analog front-end receiver for reducing indoor ambient light noise.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Live demonstration: MINDS - Meshed and internet networked devices system for smart home: Track selection: Embedded systems.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Optimized hardware algorithm for integer cube root calculation and its efficient architecture.
Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

2014
A register-free and homogenous architecture for square root algorithm.
Proceedings of the 2014 International Conference on Computer, 2014

2011
The efficient mCBE algorithm and quantization numbers for multiplierless and low complexity DCT/IDCT Image Compression Architecture.
Proceedings of the International Conference on Electrical Engineering and Informatics, 2011


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