Semeen Rehman
Orcid: 0000-0002-8972-0949
According to our database1,
Semeen Rehman
authored at least 86 papers
between 2011 and 2024.
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Bibliography
2024
Optimizing Industrial IoT Data Security Through Blockchain-Enabled Incentive-Driven Game Theoretic Approach for Data Sharing.
IEEE Access, 2024
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis.
IEEE Access, 2024
Exploring Deep Federated Learning for the Internet of Things: A GDPR-Compliant Architecture.
IEEE Access, 2024
2023
Improved angelization technique against background knowledge attack for 1:M microdata.
PeerJ Comput. Sci., 2023
Proceedings of the 19th International Conference on Wireless and Mobile Computing, 2023
2022
High-Performance Accurate and Approximate Multipliers for FPGA-Based Hardware Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ForASec: Formal Analysis of Hardware Trojan-Based Security Vulnerabilities in Sequential Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
CoRR, 2022
IEEE Access, 2022
IEEE Access, 2022
Proceedings of the 18th International Conference on Wireless and Mobile Computing, 2022
Towards Multi-Level Modelling and Monitoring of Real-time Personalised Health Conditions.
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology.
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
AID: Accuracy Improvement of Analog Discharge-Based in-SRAM Multiplication Accelerator.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Computers, 2021
BioNetExplorer: Architecture-Space Exploration of Biosignal Processing Deep Neural Networks for Wearables.
IEEE Internet Things J., 2021
BioNetExplorer: Architecture-Space Exploration of Bio-Signal Processing Deep Neural Networks for Wearables.
CoRR, 2021
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Des. Test, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
2019
CoRR, 2019
Architectural-Space Exploration of Heterogeneous Reliability and Checkpointing Modes for Out-of-Order Superscalar Processors.
IEEE Access, 2019
MemGANs: Memory Management for Energy-Efficient Acceleration of Complex Computations in Hardware Architectures for Generative Adversarial Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
Studying Aging and Soft Error Mitigation Jointly under Constrained Scenarios in Multi-Cores.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
TrISec: Training Data-Unaware Imperceptible Security Attacks on Deep Neural Networks.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
QuSecNets: Quantization-based Defense Mechanism for Securing Deep Neural Network against Adversarial Attacks.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
FAdeML: Understanding the Impact of Pre-Processing Noise Filtering on Adversarial Machine Learning.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
TrojanZero: Switching Activity-Aware Design of Undetectable Hardware Trojans with Zero Power and Area Footprint.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Building Robust Machine Learning Systems: Current Progress, Research Challenges, and Opportunities.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
Approximate Multi-Accelerator Tiled Architecture for Energy-Efficient Motion Estimation.
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
Proceedings of the Approximate Circuits, Methodologies and CAD., 2019
2018
X-DNNs: Systematic Cross-Layer Approximations for Energy-Efficient Deep Neural Networks.
J. Low Power Electron., 2018
CoRR, 2018
Heterogeneous Reliability Modes with Efficient State Compression for Out-of-Order Superscalar Processors.
CoRR, 2018
A Methodology for Automatic Selection of Activation Functions to Design Hybrid Deep Neural Networks.
CoRR, 2018
SSCNets: A Selective Sobel Convolution-based Technique to Enhance the Robustness of Deep Neural Networks against Security Attacks.
CoRR, 2018
ISA4ML: Training Data-Unaware Imperceptible Security Attacks on Machine Learning Modules of Autonomous Vehicles.
CoRR, 2018
MPNA: A Massively-Parallel Neural Array Accelerator with Dataflow Optimization for Convolutional Neural Networks.
CoRR, 2018
Robustness for Smart Cyber Physical Systems and Internet-of-Things: From Adaptive Robustness Methods to Reliability and Security for Machine Learning.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Security for Machine Learning-Based Systems: Attacks and Challenges During Training and Inference.
Proceedings of the 2018 International Conference on Frontiers of Information Technology, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
An overview of next-generation architectures for machine learning: Roadmap, opportunities and challenges in the IoT era.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding.
IEEE Trans. Computers, 2017
Embracing approximate computing for energy-efficient motion estimation in high efficiency video coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-cores.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
IEEE Trans. Computers, 2016
Task Mapping for Redundant Multithreading in Multi-Cores with Reliability and Performance Heterogeneity.
IEEE Trans. Computers, 2016
IEEE Des. Test, 2016
Cross-Layer Reliability Modeling and Optimization: Compiler and Run-Time System Interactions.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
ageOpt-RMT: compiler-driven variation-aware aging optimization for redundant multithreading.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Springer, ISBN: 978-3-319-25770-9, 2016
2015
DRVS: Power-efficient reliability management through Dynamic Redundancy and Voltage Scaling under variations.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
ACSEM: accuracy-configurable fast soft error masking analysis in combinatorial circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
dsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
R<sup>2</sup>Cache: Reliability-aware reconfigurable last-level cache architecture for multi-cores.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Compiler-driven dynamic reliability management for on-chip systems under variabilities.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
dTune: Leveraging Reliable Code Generation for Adaptive Dependability Tuning under Process Variation and Aging-Induced Effects.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
Reliable code generation and execution on unreliable hardware under joint functional and timing reliability considerations.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013
DHASER: dynamic heterogeneous adaptation for soft-error resiliency in ASIP-based multi-core systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Leveraging variable function resilience for selective software reliability on unreliable hardware.
Proceedings of the Design, Automation and Test in Europe, 2013
CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.
Proceedings of the Design, Automation and Test in Europe, 2013
Exploiting program-level masking and error propagation for constrained reliability optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Revc: Computationally Reliable Video Coding on unreliable hardware platforms: A case study on error-tolerant H.264/AVC CAVLC entropy coding.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Reliable software for unreliable hardware: embedded code generation aiming at reliability.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011