Radu Muresan

According to our database1, Radu Muresan authored at least 24 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Mixed-Signal Physically Unclonable Function With CMOS Capacitive Cells.
IEEE Access, 2019

Chaotic Encryption Algorithm With Key Controlled Neural Networks for Intelligent Transportation Systems.
IEEE Access, 2019

Design of Chaotic Block Cipher Operation Mode for Intelligent Transportation Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Improving the Security of Cloud-Based Intelligent Transportation Systems.
Proceedings of the 2019 IEEE Canadian Conference of Electrical and Computer Engineering, 2019

2018
Image-Based Visibility Estimation Algorithm for Intelligent Transportation Systems.
IEEE Access, 2018

2017
An overview of hardware-level statistical power analysis attack countermeasures.
J. Cryptogr. Eng., 2017

Capacitive physically unclonable function.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

IoT-based multifunctional Scalable real-time Enhanced Road Side Unit for Intelligent Transportation Systems.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Implementation of a decoupling based power analysis attack countermeasure.
IET Circuits Devices Syst., 2016

2014
On-Chip Nanoscale Capacitor Decoupling Architectures for Hardware Security.
IEEE Trans. Emerg. Top. Comput., 2014

Modeling the effect of NMOS gate capacitance in an on-chip decoupling capacitor PAA countermeasure.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013
Hilbert-Huang Transform for Feature Extraction of temperature modulated MOS sensors.
Int. J. Inf. Acquis., 2013

On-chip decoupling architecture with variable nMOS gate capacitance for security protection.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2012
Integrated capacitor switchbox for security protection.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
The effectiveness of a current flattening circuit as countermeasure against DPA attacks.
Microelectron. J., 2011

2009
On-Chip Power-Efficient Current Flattening Circuit.
J. Circuits Syst. Comput., 2009

2008
Protection Circuit against Differential Power Analysis Attacks for Smart Cards.
IEEE Trans. Computers, 2008

2006
On-chip current flattening circuit with dynamic voltage scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Instantaneous current modeling in a complex VLIW processor core.
ACM Trans. Embed. Comput. Syst., 2005

An integrated current flattening module for embedded cryptosystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Power-smart system-on-chip architecture for embedded cryptosystems.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Current flattening in software and hardware for security applications.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2001
Current consumption dynamics at instruction and program level for a <i>VLIW</i> DSP processor.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.
Proceedings of the SOC Design Methodologies, 2001


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