Raghu Sastry

According to our database, Raghu Sastry authored at least 14 papers between 1992 and 1998.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1998

A VLSI Architecture for Approximate Tree Matching.

Raghu Sastry, N. Ranganathan

IEEE Trans. Computers, 1998

SMAC: A VLSI Architecture for Scene Matching.

N. Ranganathan, Raghu Sastry, Raguveer Venkatesan

Real Time Imaging, 1998

1996

A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip.

Albert Mu, Jeff Larson, Raghu Sastry, Thomas Wicki, Winfried W. Wilcke

Proceedings of the Forty-First IEEE Computer Society International Conference: Technologies for the Information Superhighway, 1996

1995

CASM: A VLSI Chip for Approximate String Matching.

Raghu Sastry, N. Ranganathan, Klinton Remedios

IEEE Trans. Pattern Anal. Mach. Intell., 1995

VLSI Architectures for High-Speed Range Estimation.

Raghu Sastry, N. Ranganathan, Ramesh C. Jain

IEEE Trans. Pattern Anal. Mach. Intell., 1995

PMAC: A Polygon Matching Chip.

Raghu Sastry, N. Ranganathan

Int. J. Pattern Recognit. Artif. Intell., 1995

A VLSI Architecture for Computer the Tree-to-Tree Distance.

Raghu Sastry, N. Ranganathan

Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994

VLSI Architectures for Pattern Matching.

N. Ranganathan, Raghu Sastry

Int. J. Pattern Recognit. Artif. Intell., 1994

1993

VLSI architectures for polygon recognition.

Raghu Sastry, N. Ranganathan, Horst Bunke

IEEE Trans. Very Large Scale Integr. Syst., 1993

Hardware Algorithms for Polygon Matching.

Raghu Sastry, N. Ranganathan, Horst Bunke

Proceedings of the Sixth International Conference on VLSI Design, 1993

VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis.

Raghu Sastry, N. Ranganathan, Ramesh C. Jain

Proceedings of the Seventh International Parallel Processing Symposium, 1993

A Systolic Array for Approximate String Matching.

Raghu Sastry, N. Ranganathan

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

SMAC: A Scene Matching Chip.

N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992

A VLSI architecture for hierarchical scene matching.

R. Venkatesan, Raghu Sastry, N. Ranganathan

Proceedings of the 11th IAPR International Conference on Pattern Recognition, 1992