Rahebeh Niaraki Asli

According to our database, Rahebeh Niaraki Asli authored at least 7 papers between 2013 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

An efficient power and accuracy trade-off in error-resilient applications using approximate multipliers with error correction.

Pegah Zakian, Rahebeh Niaraki Asli

J. Supercomput., June, 2026

2020

An efficient design of low-power and high-speed approximate compressor in FinFET technology.

Pegah Zakian, Rahebeh Niaraki Asli

Comput. Electr. Eng., 2020

2019

A new 7T SRAM cell in sub-threshold region with a high performance and small area with bit interleaving capability.

Maryam Nobakht, Rahebeh Niaraki Asli

IET Circuits Devices Syst., 2019

Impact of Negative Bias Temperature Instability on Gate-All-Around Flip-Flops.

Shiva Taghipour, Rahebeh Niaraki Asli

J. Electron. Test., 2019

2017

Aging comparative analysis of high-performance FinFET and CMOS flip-flops.

Shiva Taghipour, Rahebeh Niaraki Asli

Microelectron. Reliab., 2017

A Near-Threshold Soft Error Resilient 7T SRAM Cell with Low Read Time for 20 nm FinFET Technology.

Rahebeh Niaraki Asli, Shiva Taghipour

J. Electron. Test., 2017

2013

High Efficiency Time Redundant Hardened Latch for Reliable Circuit Design.

Rahebeh Niaraki Asli, Saeideh Shirinzadeh

J. Electron. Test., 2013