Rahul Chaurasia
Orcid: 0000-0001-5763-8601
According to our database1,
Rahul Chaurasia
authored at least 25 papers
between 2021 and 2024.
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Bibliography
2024
Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP Against Piracy.
SN Comput. Sci., December, 2024
IEEE Des. Test, October, 2024
Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS.
Integr., March, 2024
HLS based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2024
SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2024
Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2024
2023
Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs.
Comput. Electr. Eng., October, 2023
IEEE Trans. Consumer Electron., August, 2023
Robust Security of Hardware Accelerators Using Protein Molecular Biometric Signature and Facial Biometric Encryption Key.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023
Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.
Comput. Electr. Eng., January, 2023
IEEE Trans. Dependable Secur. Comput., 2023
Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis.
Microprocess. Microsystems, 2023
Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller's Fingerprint Encrypted Amino Acid Biometric Sample.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023
2022
Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric.
IEEE Trans. Consumer Electron., 2022
Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems.
IEEE Consumer Electron. Mag., 2022
Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression.
IEEE Access, 2022
Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
IEEE Trans. Consumer Electron., 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021