Mahendra Rathor

According to our database, Mahendra Rathor authored at least 23 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Hard-Sign: A Hardware Watermarking Scheme Using Dated Handwritten Signature.

Mahendra Rathor, Girraj Prasad Rathor

IEEE Des. Test, 2024

Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment.

Akash Panzade, Deepak Kumar, Mahendra Rathor, Urbi Chatterjee

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

Quadruple phase watermarking during high level synthesis for securing reusable hardware intellectual property cores.

Mahendra Rathor, Aditya Anshul, K. Bharath, Rahul Chaurasia, Anirban Sengupta

Comput. Electr. Eng., January, 2023

Exploring Handwritten Signature Image Features for Hardware Security.

Mahendra Rathor, Anirban Sengupta, Rahul Chaurasia, Aditya Anshul

IEEE Trans. Dependable Secur. Comput., 2023

Biometrics for Hardware Security and Trust: Discussion and Analysis.

Anirban Sengupta, Mahendra Rathor, Rahul Chaurasia

IT Prof., 2023

Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers.

Mahendra Rathor, Vishesh Mishra, Urbi Chatterjee

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Sorting Attacks Resilient Authentication Protocol for CMOS Image Sensor Based PUF.

Chandan Kumar, Mahendra Rathor, Urbi Chatterjee

IACR Cryptol. ePrint Arch., 2022

Dual-Tone Multi-Frequency Assisted Acoustic Side Channel Attack to Retrieve Dialled Call Log.

Abhishek Revskar, Mahendra Rathor, Urbi Chatterjee

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2022

Hardware (IP) Watermarking During Behavioral Synthesis.

Anirban Sengupta, Mahendra Rathor

Behavioral Synthesis for Hardware Security, 2022

2021

Facial Biometric for Securing Hardware Accelerators.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Very Large Scale Integr. Syst., 2021

Signature Biometric based Authentication of IP Cores for Secure Electronic Systems.

Mahendra Rathor, Anirban Sengupta

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020

Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Very Large Scale Integr. Syst., 2020

Obfuscated Hardware Accelerators for Image Processing Filters - Application Specific and Functionally Reconfigurable Processors.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Consumer Electron., 2020

Enhanced Security of DSP Circuits Using Multi-Key Based Structural Obfuscation and Physical-Level Watermarking for Consumer Electronics Systems.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Consumer Electron., 2020

IP Core Steganography Using Switch Based Key-Driven Hash-Chaining and Encoding for Securing DSP Kernels Used in CE Systems.

Mahendra Rathor, Anirban Sengupta

IEEE Trans. Consumer Electron., 2020

Structural Obfuscation and Crypto-Steganography-Based Secured JPEG Compression Hardware for Medical Imaging Systems.

Anirban Sengupta, Mahendra Rathor

IEEE Access, 2020

Securing IP Cores in CE Systems using Key-driven Hash-chaining based Steganography.

Mahendra Rathor, Pallabi Sarkar, Vipul Kumar Mishra, Anirban Sengupta

Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020

2019

IP Core Steganography for Protecting DSP Kernels Used in CE Systems.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Consumer Electron., 2019

Protecting DSP Kernels Using Robust Hologram-Based Obfuscation.

Anirban Sengupta, Mahendra Rathor

IEEE Trans. Consumer Electron., 2019

Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware.

Anirban Sengupta, Mahendra Rathor

IEEE Access, 2019

Robust Logic locking for Securing Reusable DSP Cores.

Mahendra Rathor, Anirban Sengupta

IEEE Access, 2019

Improved Delay Estimation Model for Loop based DSP cores.

Anirban Sengupta, Mahendra Rathor

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

Enhanced Functional Obfuscation of DSP core using Flip-Flops and Combinational logic.

Mahendra Rathor, Anirban Sengupta

Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019