Rainer Kress

According to our database, Rainer Kress authored at least 27 papers between 1992 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Panel: The world is going... analog & mixed-signal! What about EDA?

Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2012

Panel: What is EDA doing for trailing edge technologies?

Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2000

Role-Centered Conceptual Modeling in System Design.

Michael Mrva, Rainer Kress

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Frankfurt, Germany, February 28, 2000

FPGA-Based Prototyping for Product Definition.

Rainer Kress, Andreas Pyttel, Alexander Sedlmeier

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

Debugging Application-Specific Programmable Products.

Rainer Kress, Andreas Pyttel

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components.

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress

Proceedings of the 1999 Design, 1999

Java Driven Codesign and Prototyping of Networked Embedded Systems.

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress

Proceedings of the 36th Conference on Design Automation, 1999

1998

High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems.

Rainer Kress, Andreas Pyttel

Proceedings of the Field-Programmable Logic and Applications, 1998

A Scalable Architecture for Multi-threaded JAVA Applications.

Michael Mrva, Klaus Buchenrieder, Rainer Kress

Proceedings of the 1998 Design, 1998

A hardware/software prototyping environment for dynamically reconfigurable embedded systems.

Josef Fleischmann, Klaus Buchenrieder, Rainer Kress

Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

1997

An operating system for custom computing machines based on the Xputer paradigm.

Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

1996

High-performance computing using a reconfigurable accelerator.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig

Concurr. Pract. Exp., 1996

CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Partitioning Programming Environment for a Novel Parallel Architecture.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of IPPS '96, 1996

Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Field-Programmable Logic, 1996

An Embedded Accelerator for Real-Time Image Processing.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

Two-Level Hardware/Software Partitioning Using CoDe-X.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

A Synthesis System For Bus-Based Wavefront Array Architectures.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

A fast reconfigurable ALU for Xputers.

Rainer Kress

PhD thesis, 1996

1995

A datapath synthesis system for the reconfigurable datapath architecture.

Reiner W. Hartenstein, Rainer Kress

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A Parallelizing Compilation Method for the Map-oriented Machine.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

A New FPGA Architecture for Word-Oriented Datapaths.

Reiner W. Hartenstein, Rainer Kress, Helmut Reinig

Proceedings of the Field-Programmable Logic, 1994

Data-Procedural Languages for FPL-based Machines.

Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the Field-Programmable Logic, 1994

A dynamically reconfigurable wavefront array architecture for evaluation of expressions.

Reiner W. Hartenstein, Rainer Kress, Helmut Reinig

Proceedings of the International Conference on Application Specific Array Processors, 1994

1993

CMOS interconnect modelling for timing analysis.

Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana

Microprocess. Microprogramming, 1993

1992

Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods.

Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992