Reiner W. Hartenstein

According to our database, Reiner W. Hartenstein authored at least 108 papers between 1970 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

The tunnel vision syndrome: Massively delaying progress.

Reiner W. Hartenstein

Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2008

The von Neumann Syndrome and the CS Education Dilemma.

Reiner W. Hartenstein

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

The Neumann Syndrome calls for a revolution.

Reiner W. Hartenstein

Proceedings of the 1st international workshop on High-performance reconfigurable computing technology and applications, 2007

2006

Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic.

Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein

ACM Trans. Design Autom. Electr. Syst., 2006

Mehr Effizienz durch Configware: auch für Supercomputing.

Reiner W. Hartenstein

Prax. Inf.verarb. Kommun., 2006

The re-definition of low power design for HPC: a paradigm shift.

Reiner W. Hartenstein

Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures.

Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Flexibility and low power: a contradiction in terms?

Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson

Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

RAW keynote 2: new horizons of very high performance computing (VHPC): hurdles and chances.

Reiner W. Hartenstein

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

From Equation to VHDL: Using Rewriting Logic for Automated Function Generation.

Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

From Organic Computing to Reconfigurable Supercomputing.

Reiner W. Hartenstein

Proceedings of the ARCS 2006, 2006

Morphware and Configware.

Reiner W. Hartenstein

Proceedings of the Handbook of Nature-Inspired and Innovative Computing, 2006

2005

FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations.

Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004

Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming.

Ricardo P. Jacobi, Mauricio Ayala-Rincón, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein

Proceedings of the III Brazilian Workshop on Bioinformatics, 2004

The changing role of computer architecture education within CS curricula: invited presentation.

Reiner W. Hartenstein

Proceedings of the 2004 workshop on Computer architecture education, 2004

Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic.

Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

The digital divide of computing.

Reiner W. Hartenstein

Proceedings of the First Conference on Computing Frontiers, 2004

2003

Configware and morphware going mainstream.

Jürgen Becker, Reiner W. Hartenstein

J. Syst. Archit., 2003

Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments.

Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein

Proceedings of the 23rd International Conference of the Chilean Computer Science Society (SCCC 2003), 2003

Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic.

Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein

Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Are We Really Ready for the Breakthrough?

Reiner W. Hartenstein

Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing.

Mauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein

Proceedings of the Forum on specification and Design Languages, 2003

2002

Architectural Specification, Exploration and Simulation Through Rewriting-Logic.

Mauricio Ayala-Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos

Rev. Colomb. de Computación, 2002

Applying ELAN Strategies in Simulating Processors over Simple Architectures.

Mauricio Ayala-Rincón, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein

Proceedings of the 2nd International Workshop on Reduction Strategies in Rewriting and Programming, 2002

Memory addressing organization for stream-based reconfigurable computing.

Michael Herz, Reiner W. Hartenstein, Miguel Miranda, Erik Brockmeyer, Francky Catthoor

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Trends in reconfigurable logic and reconfigurable computing.

Reiner W. Hartenstein

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Disruptive Trends by Data-Stream-Based Computing.

Reiner W. Hartenstein

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Reconfigurable Computing: A New Business Model and its Impact on SoC Design.

Reiner W. Hartenstein

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

A decade of reconfigurable computing: a visionary retrospective.

Reiner W. Hartenstein

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Coarse grain reconfigurable architecture (embedded tutorial).

Reiner W. Hartenstein

Proceedings of ASP-DAC 2001, 2001

2000

Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures.

Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Integrated Circuit Design, 2000

Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 2000

Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract).

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of ASP-DAC 2000, 2000

1999

Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction.

Reiner W. Hartenstein, Veljko M. Milutinovic

Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

An Internet Based Development Framework for Reconfigurable Computing.

Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

Mapping Applications onto Reconfigurable Kress Arrays.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998

Real-Time Prototyping in Microprocessor/Accelerator Symbiosis.

Jürgen Becker, Reiner W. Hartenstein

Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

On Reconfigurable Co-processing Units.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

Introduction to the Configware Minitrack: Hardware and Software Come Closer.

Reiner W. Hartenstein

Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators.

Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 1998

Designing for Xilinx XC6200 FPGAs.

Reiner W. Hartenstein, Michael Herz, Frank Gilbert

Proceedings of the Field-Programmable Logic and Applications, 1998

Parallelization in Co-Compilation for Configurable Accelerators.

Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger

Proceedings of the ASP-DAC '98, 1998

1997

Seeking Solutions in Configurable Computing.

William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg

Computer, 1997

Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators.

Reiner W. Hartenstein, Jürgen Becker

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators.

Reiner W. Hartenstein, Jürgen Becker

Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

An operating system for custom computing machines based on the Xputer paradigm.

Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Data scheduling to increase performance of parallel accelerators.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators.

Reiner W. Hartenstein, Jürgen Becker

Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

A Novel Sequencer Hardware for Application Specific Computing.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997

A Novel Universal Sequencer Hardware.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger

Proceedings of the Architektur von Rechensystemen, Arbeitsteilige Systemarchitekturen: Konzepte, Lösungen, Anwendungen, Trends, 1997

1996

High-performance computing using a reconfigurable accelerator.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig

Concurr. Pract. Exp., 1996

CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Partitioning Programming Environment for a Novel Parallel Architecture.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of IPPS '96, 1996

Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Field-Programmable Logic, 1996

An Embedded Accelerator for Real-Time Image Processing.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Eighth Euromicro Workshop on Real-Time Systems, 1996

Two-Level Hardware/Software Partitioning Using CoDe-X.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996

Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress

Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

A Synthesis System For Bus-Based Wavefront Array Architectures.

Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger

Proceedings of the 1996 International Conference on Application-Specific Systems, 1996

Null Bock auf High Tech - Arbeitsplatz-Export: nur weil die Löhne zu hoch sind?

Reiner W. Hartenstein

IT Press, ISBN: 978-3-929814-06-4, 1996

1995

Custom Computing Machines - Das aktuelle Schlagwort

Reiner W. Hartenstein

Inform. Spektrum, 1995

Hardware/Software Co-Design - Das aktuelle Schlagwort

Reiner W. Hartenstein

Inform. Spektrum, 1995

Combining structural and procedural programming by parallelizing compilation.

Reiner W. Hartenstein, Karin Schmidt

Proceedings of the 1995 ACM symposium on applied computing, 1995

A datapath synthesis system for the reconfigurable datapath architecture.

Reiner W. Hartenstein, Rainer Kress

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

A Parallelizing Compilation Method for the Map-oriented Machine.

Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994

A New FPGA Architecture for Word-Oriented Datapaths.

Reiner W. Hartenstein, Rainer Kress, Helmut Reinig

Proceedings of the Field-Programmable Logic, 1994

Data-Procedural Languages for FPL-based Machines.

Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the Field-Programmable Logic, 1994

A dynamically reconfigurable wavefront array architecture for evaluation of expressions.

Reiner W. Hartenstein, Rainer Kress, Helmut Reinig

Proceedings of the International Conference on Application Specific Array Processors, 1994

Wozu noch Mikro-Chips? - Einführung in Methoden der Technischen Informatik zur Anwendung der Mikroelektronik für die Wettbewerbsfähigkeit unserer Wirtschaft: Sachbuch und Textbuch.

Reiner W. Hartenstein

Geschichte der verpaßten Gelegenheiten: Standort Deutschland, IT Press, ISBN: 978-3-929814-00-2, 1994

1993

CMOS interconnect modelling for timing analysis.

Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana

Microprocess. Microprogramming, 1993

1992

A novel paradigm of parallel computation and its use to implement simple high-performance hardware.

Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Schmidt, M. Weber

Future Gener. Comput. Syst., 1992

An Information Model Describing the Exchange of IC Technology Data.

Joachim Blödel, Markus Brandstetter, Peter Conradi, Walter Drangmeister, Reiner W. Hartenstein, Dietmar Schroeder

Proceedings of the Electronic Design Automation Frameworks: When will the promise be realized? Proceedings of the Third IFIP WG10.2/WG10.5 Workshop on Electronic Design Automation Frameworks in cooperation with GI/ITG FG 3.5.6/5.2.6 Bad Lippspringe, 1992

Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods.

Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt

Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992

1991

Gemeinsame Stellungnahme der Fakultätentage Elektrotechnik und Informatik zur Abstimmung ihrer Fachgebierte im Bereich Informationstechnik.

Franz-Josef Brandenburg, Werner Freise, Winfried Görke, Reiner W. Hartenstein, P. Kühn, H. J. Schmitt

Inform. Spektrum, 1991

1990

Xputer use in image processing and digital signal processing.

Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Lemmert, Michael Riedmüller, Karin Schmidt, M. Weber

Proceedings of the Visual Communications and Image Processing '90: Fifth in a Series, 1990

Xputers: very high throughput by innovative computing principles.

Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber

Proceedings of the Next Decade in Information Technology: Proceedings of the 5th Jerusalem Conference on Information Technology 1990, 1990

The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration.

Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber

Proceedings of the 1990 International Conference on Parallel Processing, 1990

Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing.

Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Riedmüller, Karin Schmidt, M. Weber

Proceedings of the Mustererkennung 1990, 1990

A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware.

Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber

Proceedings of the CONPAR 90, 1990

Xputers: An Open Family of Non-Von Neumann Architectures.

Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber

Proceedings of the Architektur von Rechensystemen, 1990

1989

Synthesis of systolic architectures using the SYS³ system.

Reiner W. Hartenstein, Karin Lemmert, Michael Riedmüller

Microprocessing and Microprogramming, 1989

Explicit fault modeling and hierarchical test pattern generation in the KARATE system.

Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko

Microprocessing and Microprogramming, 1989

1988

Microelectronics: VLSI design tools I.

Reiner W. Hartenstein

Microprocess. Microprogramming, 1988

A technology description method for generalized layout / circuit relations.

Joachim Blödel, Reiner W. Hartenstein, Wolfgang Nebel, Michael Ryba

Microprocess. Microprogramming, 1988

The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level Descriptions.

Gerold Affs, Reiner W. Hartenstein, Andrea Wodtko

Proceedings of the Proceedings International Test Conference 1988, 1988

The KARL/KARATE system - integrating functional test development into a CAD environment for VLSI.

Gerold Alfs, Reiner W. Hartenstein, Andrea Wodtko

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Partitionierungsschemata für Rechnerstrukturen.

Reiner W. Hartenstein, Michael Ryba

Proceedings of the GI, 1988

MLED - Ein Mehrebenen Graphik Editor für den VLSI-Entwurf.

Reiner W. Hartenstein, K. W. Jörg, Udo Welters

Proceedings of the GI, 1988

1987

MLED: A multiple abstraction level graphical editor.

Reiner W. Hartenstein, Udo Welters

Microprocess. Microprogramming, 1987

A flexible architecture for image processing.

Reiner W. Hartenstein, Alexander Hirschbiel, M. Weber

Microprocess. Microprogramming, 1987

Mehrebenenen-Graphik-Editor MLED als DBMS für VLSI-Simulation.

Reiner W. Hartenstein, Udo Welters

Proceedings of the Simulationstechnik, 1987

1983

Silicon Compiler - Das aktuelle Schlagwort.

Reiner W. Hartenstein

Inform. Spektrum, 1983

1982

KARL-II - eine Sprache zur Spezifikation beim Entwurf Kundenspezifischer Digitalbausteine.

Reiner W. Hartenstein

Angew. Inform., 1982

Die "Neue Mikroelektronik" in der Informatik: Voraussetzungen und Auswirkungen.

Reiner W. Hartenstein

Proceedings of the GI - 12. Jahrestagung, Kaiserslautern, 5. -7. Oktober 1982, Proceedings, 1982

1981

VLSI-Algorithmen - Das aktuelle Schlagwort.

Reiner W. Hartenstein

Inform. Spektrum, 1981

1980

VLSI-Bausteine in geringen Stückzahlen für Spezial-Anwendungen.

Reiner W. Hartenstein

Elektron. Rechenanlagen, 1980

Ein Compiler für die Register Transfer-Sprache KARL-2.

Reiner W. Hartenstein, Peter Liell

Proceedings of the GI - 10. Jahrestagung, Saarbrücken, 30. September, 1980

Software-Zuverlässigkeit mit Rechnernetz-Baukästen verteilter Programmierung.

J. Dieckmann, Reiner W. Hartenstein, Werner Konrad

Proceedings of the Hardware für Software, 1980

1977

Fundamentals of Structured Hardware Design.

Reiner W. Hartenstein

North-Holland, ISBN: 978-0-444-85007-2, 1977

1974

Letter to membership from incoming chairman (CAN, Oct. 73).

Reiner W. Hartenstein

SIGARCH Comput. Archit. News, 1974

Microprogramming concepts - a step towards structured hardware design.

Reiner W. Hartenstein

Proceedings of the Conference record of the 7th annual workshop on Microprogramming, 1974

Konzepte der Mikroprogrammierung.

Reiner W. Hartenstein

Proceedings of the Fachtagung Struktur und Betrieb von Rechensystemen, 1974

1973

A microprogrammable display processor concept.

Reiner W. Hartenstein, Klaus D. Mueller

Proceedings of the Conference record of the 6th annual workshop on Microprogramming, 1973

Increasing Hardware Complexity - A Challenge to Computer Architecture Education.

Reiner W. Hartenstein

Proceedings of the 1st Annual Symposium on Computer Architecture, 1973

Hierarchy of Interpreters for Modelling Complex Digital Systems.

Reiner W. Hartenstein

Proceedings of the Gesellschaft für Informatik e.V., 1973

1972

Experimentiersystem für ein technisches Informatikpraktikum.

Reiner W. Hartenstein

Proceedings of the Gesellschaft für Informatik e.V., 1972

1971

Synthese endlicher Automaten bei Problemen der Erkennung, Klassifikation und Informationsreduktion.

Reiner W. Hartenstein

J. Inf. Process. Cybern., 1971

1970

Suchlistenstrukturen zur Darstellung gerichteter Graphen und deren Anwendung bei Synthese und Minimierung spezieller endlicher Automaten.

Reiner W. Hartenstein

Elektron. Rechenanlagen, 1970