Helmut Reinig

According to our database1, Helmut Reinig authored at least 17 papers between 1992 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2014
Deterministic Synthesis of Hybrid Application-Specific Network-on-Chip Topologies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
A spectral clustering approach to application-specific network-on-chip synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Automated construction of a cycle-approximate transaction level model of a memory controller.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

2010
Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks.
Proceedings of the NOCS 2010, 2010

2009
NoC topology exploration for mobile multimedia applications.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures.
Proceedings of the Proceedings 41st Annual Simulation Symposium (ANSS-41 2008), 2008

1999
A scalable architecture for custom computing.
PhD thesis, 1999

1998
Codevelopment of long haul ISDN transceiver and design methodology improves time to market.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

1996
High-performance computing using a reconfigurable accelerator.
Concurr. Pract. Exp., 1996

CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

1995
A Parallelizing Compilation Method for the Map-oriented Machine.
Proceedings of the International Conference on Application Specific Array Processors (ASAP'95), 1995

1994
A New FPGA Architecture for Word-Oriented Datapaths.
Proceedings of the Field-Programmable Logic, 1994

Data-Procedural Languages for FPL-based Machines.
Proceedings of the Field-Programmable Logic, 1994

A dynamically reconfigurable wavefront array architecture for evaluation of expressions.
Proceedings of the International Conference on Application Specific Array Processors, 1994

1992
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods.
Proceedings of the Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Second International Workshop on Field-Programmable Logic and Applications, Vienna, Austria, August 31, 1992


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