Rajarshee P. Bharadwaj

According to our database1, Rajarshee P. Bharadwaj authored at least 5 papers between 2005 and 2006.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2006
Exploring Logic Block Granularity in Leakage Tolerant FPGA.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A leakage aware design methodology for power-gated programmable architectures.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005
FPGA Architecture for Standby Power Management.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Next Generation Architectures and CAD for Power Aware Programmable Fabrics.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploiting temporal idleness to reduce leakage power in programmable architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005


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