Dinesh Bhatia

Orcid: 0000-0002-5019-7417

According to our database1, Dinesh Bhatia authored at least 84 papers between 1990 and 2023.

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Bibliography

2023
Machine learning based fast and accurate High Level Synthesis design space exploration: From graph to synthesis.
Integr., 2023

Feed Forward Neural Network BCI-based trajectory-controlled Lower-limb exoskeleton: a Biomechatronics Approach, 430-440.
Int. J. Robotics Autom., 2023

Application of Machine Learning in FPGA EDA Tool Development.
IEEE Access, 2023

Enhancing Student Engagement in Engineering and Education Through Virtual Reality: A Survey-Based Analysis.
Proceedings of the IEEE Region 10 Conference, 2023

2022
Robust Estimation of FPGA Resources and Performance from CNN Models.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

PPA Based CNN Architecture Explorer.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

MLSBench: A Benchmark Set for Machine Learning based FPGA HLS Design Flows.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Predicting Post-Route Quality of Results Estimates for HLS Designs using Machine Learning.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021
An Automated Tool for Implementing Deep Neural Networks on FPGA.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Resource and Performance Estimation for CNN Models using Machine Learning.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2020
Empirical greedy machine-based automatic liver segmentation in CT images.
IET Image Process., 2020

Automated Floorplanning for Partially Reconfigurable Designs on Heterogenrous FPGAs.
CoRR, 2020

MLSBench: A Synthesizable Dataset of HLS Designs to Support ML Based Design Flows.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2017
Portable impedance measurement device for sweat based glucose detection.
Proceedings of the 14th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2017

2016
Comparison of muscle activation patterns among healthy males and females during different lower limb movements.
Int. J. Medical Eng. Informatics, 2016

Floorplanning of Partially Reconfigurable Design on Heterogeneous FPGA (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2014
Design of smart functional electric stimulator for physically challenged person.
Int. J. Medical Eng. Informatics, 2014

A smart door access system using finger print biometric system.
Int. J. Medical Eng. Informatics, 2014

Quantitative measurement of carbon monoxide level in closed environment.
Int. J. Medical Eng. Informatics, 2014

2013
Impact of communication technology on human brain activity: mobile phone vs. landline phone.
Int. J. Medical Eng. Informatics, 2013

Growth of neural engineering and neuro-mechanics in India: physically challenged looking towards a bright future.
Int. J. Medical Eng. Informatics, 2013

Antenna designs for wearable body sensor communication.
Proceedings of the 6th International Conference on PErvasive Technologies Related to Assistive Environments, 2013

2011
Study of performance and propagation characteristics of wire and planar structures around human body.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

2008
Power efficient multi-band contextual activity monitoring for assistive environments.
Proceedings of the 1st ACM International Conference on Pervasive Technologies Related to Assistive Environments, 2008

Early stage FPGA interconnect leakage power estimation.
Proceedings of the 26th International Conference on Computer Design, 2008

A dynamic temperature control simulation system for FPGAs.
Proceedings of the FPL 2008, 2008

2007
Thermal Modeling and Temperature Driven Placement for FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Pre-route Interconnect Capacitance and Power Estimation in FPGAs.
Proceedings of the FPL 2007, 2007

2006
Interconnect estimation for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Exploring Logic Block Granularity in Leakage Tolerant FPGA.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A leakage aware design methodology for power-gated programmable architectures.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Generic Network Interfaces for Plug and Play NoC Based Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
A priori wirelength and interconnect estimation based on circuit characteristic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

FPGA based EBCOT architecture for JPEG 2000.
Microprocess. Microsystems, 2005

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

FPGA Architecture for Standby Power Management.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Timing Aware Interconnect Prediction Models for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploiting temporal idleness to reduce leakage power in programmable architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
On metrics for comparing interconnect estimation methods for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Estimating Pre-Placement FPGA Interconnection Requirements.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003
On Using Tabu Search for Design Automation of VLSI Systems.
J. Heuristics, 2003

A-priori wirelength and interconnect estimation based on circuit characteristics.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Interconnect Estimation for FPGAs under Timing Driven Domains.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
On Routing Demand and Congestion Estimation for FPGAs.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Rapid and Reliable Routability Estimation for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2002

On metrics for comparing routability estimation methods for FPGAs.
Proceedings of the 39th Design Automation Conference, 2002

2001
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits.
Proceedings of the Field-Programmable Logic and Applications, 2001

Tightly Integrated Placement and Routing for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

2000
Resource requirements and layouts for field programmable interconnection chips.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Bounds, designs and layouts for multi-terminal FPIC architectures.
Integr., 2000

1999
Temporal Partitioning and Scheduling Data Flow Graphs for Reconfigurable Computers.
IEEE Trans. Computers, 1999

Clustering to improve bi-partition quality and run time.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Fast timing driven placement using tabu search.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Tabu Search: Ultra-Fast Placement for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

NEBULA: A Partially and Dynamically Reconfigurable Architecture.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

A Methodology for Fast FPGA Floorplanning.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

1998
Timing Driven Multi-FPGA Board Partitioning.
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Emulating Large Designs on Small Reconfigurable Hardware.
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998

Clock-skew constrained placement for row based designs.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Partitioning in time: a paradigm for reconfigurable computing.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Fast Floorplanning for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 1998

REACT: Reactive Environment for Runtime Reconfiguration.
Proceedings of the Field-Programmable Logic and Applications, 1998

Temporal Partitioning and Scheduling for Reconfigurable Computing.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997
Macro Block Based FPGA Floorplanning.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Reconfigurable Computing.
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Partitioning Under Timing and Area Constraints.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997

Performance Driven Floorplanning for FPGA Based Designs.
Proceedings of the 1997 ACM/SIGDA Fifth International Symposium on Field Programmable Gate Arrays, 1997

A constructive method for data path area estimation during high-level VLSI synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996
Greedy Segmented Channel Router.
VLSI Design, 1996

A Multi-Terminal Net Router for Field-Programmable Gate Arrays.
VLSI Design, 1996

Field-Programmable Gate Arrays.
VLSI Design, 1996

Clock-Skew Constrained Cell Placement.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Multiway Partitioner for High Performance FPGA Based Board Architecture.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

RACE: Reconfigurable and Adaptive Computing Environment.
Proceedings of the Field-Programmable Logic, 1996

1995
Pseudo-exhaustive built-in TPG for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Resource requirements for field programmable interconnection chips.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1994
Detailed Routing of Multi-Terminal Nets in FPGAs.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Hierarchical Reconfiguration of VLSI/WSI Arrays.
Proceedings of the Seventh International Conference on VLSI Design, 1994

Generalized segmented channel routing.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Mathematical model for routability analysis of FPGAs.
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
Pseudoexhaustive BIST for Sequential Circuits.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1992
Improved Algorithms for Routing on Two-Dimensional Grids.
Proceedings of the Graph-Theoretic Concepts in Computer Science, 1992

1990
Efficient Reconfiguration of WSI Arrays.
Proceedings of the First International Conference on Systems Integration, 1990


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