Poras T. Balsara

According to our database1, Poras T. Balsara authored at least 78 papers between 1987 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2014, "For contributions to the design of all-digital frequency synthesis".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM.
IEEE Trans. Industrial Electronics, 2018

2017
Analysis of Zeros in a Boost DC-DC Converter: State Diagram Approach.
IEEE Trans. on Circuits and Systems, 2017

Time-Domain Analysis of Passive Mixer Impedance: A Switched-Capacitor Approach.
IEEE Trans. on Circuits and Systems, 2017

Portable impedance measurement device for sweat based glucose detection.
Proceedings of the 14th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2017

2016
A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution.
J. Solid-State Circuits, 2016

A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation.
J. Electronic Testing, 2016

Effect of sampling time and sampling instant on the frequency response of a boost converter.
Proceedings of the IECON 2016, 2016

2015
Minimum Phase Wide Output Range Digitally Controlled SIDO Boost Converter.
IEEE Trans. on Circuits and Systems, 2015

Envelope tracking using transient waveform switching shaping supply modulation.
I. J. Circuit Theory and Applications, 2015

2014
Complex QR Decomposition Using Fast Plane Rotations for MIMO Applications.
IEEE Communications Letters, 2014

2013
Estimation of passive mixer output bandwidth using switched-capacitor techniques.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Linear Time-Variant Modeling and Analysis of All-Digital Phase-Locked Loops.
IEEE Trans. on Circuits and Systems, 2012

Hybrid NEMS-CMOS DC-DC Converter for Improved Area and Power Efficiency.
Proceedings of the 25th International Conference on VLSI Design, 2012

Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management.
Proceedings of the 25th International Conference on VLSI Design, 2012

Alien crosstalk mitigation in vectored DSL systems for backhaul applications.
Proceedings of IEEE International Conference on Communications, 2012

2011
A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter.
J. Solid-State Circuits, 2011

Improving performance of NEM relay logic circuits using integrated charge-boosting flip flop.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Multi-clock domain analysis and modeling of all-digital frequency synthesizers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
A Generic Scalable Architecture for Min-Sum/Offset-Min-Sum Unit for Irregular/Regular LDPC Decoder.
IEEE Trans. VLSI Syst., 2010

Recombination of Envelope and Phase Paths in Wideband Polar Transmitters.
IEEE Trans. on Circuits and Systems, 2010

An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter.
IEEE Trans. on Circuits and Systems, 2010

Design of a link-controller architecture for multiple serial link protocols.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2009
All Digital-Quadrature-Modulator Based Wideband Wireless Transmitters.
IEEE Trans. on Circuits and Systems, 2009

Parallel Correction and Adaptation Engines for I/Q Mismatch Compensation.
IEEE Trans. on Circuits and Systems, 2009

2008
Time-Domain Modeling of an RF All-Digital PLL.
IEEE Trans. on Circuits and Systems, 2008

2007
All-Digital PLL With Ultra Fast Settling.
IEEE Trans. on Circuits and Systems, 2007

Iterative (TURBO) IQ Imbalance Estimation and Correction in BICM-ID for Flat Fading Channels.
Proceedings of the 66th IEEE Vehicular Technology Conference, 2007

VLSI Architecture for Matrix Inversion using Modified Gram-Schmidt based QR Decomposition.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Effect of Word-length Precision on the Performance of MIMO Systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless Transmitters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless Transmitters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS.
IEEE Trans. on Circuits and Systems, 2006

IIP2 and DC Offsets in the Presence of Leakage at LO Frequency.
IEEE Trans. on Circuits and Systems, 2006

A Wide-Range, High-Resolution, Compact CMOS, Time to Digital Converter.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Exploring Logic Block Granularity in Leakage Tolerant FPGA.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

A generalized signal reconstruction method for designing interpolation filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Reconfigurable CAM Architecture for Network Search Engines.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Generic Network Interfaces for Plug and Play NoC Based Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
SoC with an integrated DSP and a 2.4-GHz RF transmitter.
IEEE Trans. VLSI Syst., 2005

Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination.
IEEE Trans. on Circuits and Systems, 2005

Event-driven Simulation and modeling of phase noise of an RF oscillator.
IEEE Trans. on Circuits and Systems, 2005

Phase-domain all-digital phase-locked loop.
IEEE Trans. on Circuits and Systems, 2005

Power Switch Network Design for MTCMOS.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

The Impact of Inductance on Transients Affecting Gate Oxide Reliability.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

VHDL Simulation and Modeling of an All-Digital RF Transmitter.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Design and Implementation of Configurable W-CDMA Rake Receiver Architectures on FPGA.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Ripple-Precharge TCAM A Low-Power Solution for Network Search Engines.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

FPGA Architecture for Standby Power Management.
Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Exploiting temporal idleness to reduce leakage power in programmable architectures.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Interconnect Modeling for Copper/Low-k Technologies.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Event-driven simulation and modeling of an RF oscillator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

PCAM: A Ternary CAM Optimized for Longest Prefix Matching Tasks.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Benchmarks for Interconnect Parasitic Resistance and Capacitance.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

2002
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

2001
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels.
IEEE Trans. VLSI Syst., 2001

Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Challenges in integrated CMOS transceivers for short distance wireless.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

2000
High-performance energy-efficient D-flip-flop circuits.
IEEE Trans. VLSI Syst., 2000

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Reconfigurable Array Media Processor (RAMP).
Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999
High performance low power array multiplier using temporal tiling.
IEEE Trans. VLSI Syst., 1999

Mini-Tutorial: Bridging the Gap between TCAD and ECAD Methodologies in Deep Sub-Micron Interconnect Extraction and Analysis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

1998
Energy optimization of multilevel cache architectures for RISC and CISC processors.
IEEE Trans. VLSI Syst., 1998

LAPLUS: An Efficient, Effective and Stable Switch Algorithm for Flow Control of the Available Bit Rate ATM Service.
Proceedings of the Proceedings IEEE INFOCOM '98, The Conference on Computer Communications, Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies, Gateway to the 21st Century, San Francisco, CA, USA, March 29, 1998

1996
Leap frog multiplier.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Design techniques for high performance, energy efficient control logic.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Short-circuit power driven gate sizing technique for reducing power dissipation.
IEEE Trans. VLSI Syst., 1995

An architecture for a DSP field-programmable gate array.
IEEE Trans. VLSI Syst., 1995

Hierarchy embedded differential image for progressive transmission using lossless compression.
IEEE Trans. Circuits Syst. Video Techn., 1995

Energy optimization of multi-level processor cache architectures.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1992
Intermediate-level vision tasks on a memory array architecture.
Mach. Vis. Appl., 1992

Design and implementation of a multi-microprocessor architecture for image processing.
Microprocessors and Microsystems - Embedded Hardware Design, 1992

1991
Image processing on a memory array architecture.
VLSI Signal Processing, 1991

Digit Serial Multipliers.
J. Parallel Distrib. Comput., 1991

1987
Systolic & semi-systolic digit serial multipliers.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987


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