Rajendra S. Katti

Affiliations:
  • University of Washington Tacoma, USA
  • North Dakota State University, Fargo, USA (former)


According to our database1, Rajendra S. Katti authored at least 61 papers between 1989 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Efficient and Private Scoring of Decision Trees, Support Vector Machines and Logistic Regression Models Based on Pre-Computation.
IEEE Trans. Dependable Secur. Comput., 2019

2016
Efficient and Private Scoring of Decision Trees, Support Vector Machines and Logistic Regression Models based on Pre-Computation.
IACR Cryptol. ePrint Arch., 2016

2015
Efficient Unconditionally Secure Comparison and Privacy Preserving Machine Learning Classification Protocols.
Proceedings of the Provable Security, 2015

2014
Road network compression techniques in spatiotemporal embedded systems: a survey.
Proceedings of the 5th ACM SIGSPATIAL International Workshop on GeoStreaming, 2014

2013
Multicast authentication in the smart grid with one-time signatures from sigma-protocols.
Proceedings of the ACM/IEEE 4th International Conference on Cyber-Physical Systems (with CPS Week 2013), 2013

MISRs for Fast Authentication of Long Messages.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
On the Security of Key-Based Interval Splitting Arithmetic Coding With Respect to Message Indistinguishability.
IEEE Trans. Inf. Forensics Secur., 2012

Secure Comparison Without Explicit XOR
CoRR, 2012

Provable Data Possession Using Sigma-protocols.
Proceedings of the 11th IEEE International Conference on Trust, 2012

Novel asynchronous registers for sequential circuits with quantum-dot cellular automata.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks.
IEEE Trans. Inf. Forensics Secur., 2011

Desynchronization: design for verification.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
Pseudorandom Bit Generation Using Coupled Congruential Generators.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

Nonce Generation For The Digital Signature Standard.
Int. J. Netw. Secur., 2010

Fast Message Authentication Code for Multiple Messages with Provable Security.
Proceedings of the Global Communications Conference, 2010

2009
Montgomery multiplication over rings.
J. Frankl. Inst., 2009

Token-Aware Completion Functions for Elastic Processor Verification.
J. Electr. Comput. Eng., 2009

Verification of Synchronous Elastic Processors.
IEEE Embed. Syst. Lett., 2009

Image Encyption using Dynamic Shuffling and XORing Processes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Verification of Desynchronized Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Security using Shannon-Fano-Elias Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Achieving network on chip fault tolerance by adaptive remapping.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

2008
Secure pseudo-random bit sequence generation using coupled linear congruential generators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs.
IEEE Trans. Computers, 2007

2006
Multiple-output low-power linear feedback shift register design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

A New Source Coding Scheme with Small Expected Length and Its Application to Simple Data Encryption.
IEEE Trans. Computers, 2006

Authentication and Key Agreement Protocols Preserving Anonymity.
Int. J. Netw. Secur., 2006

A Hash-based Strong Password Authentication Protocol with User Anonymity.
Int. J. Netw. Secur., 2006

A Secure Identification and Key agreement protocol with user Anonymity (SIKA).
Comput. Secur., 2006

An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Using Improved Shannon-Fano-Elias Codes for Data Encryption.
Proceedings of the Proceedings 2006 IEEE International Symposium on Information Theory, 2006

Algorithm and implementation of signed-binary recoding with asymmetric digit sets for elliptic curve cryptosystems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
The alternating greedy expansion and applications to computing digit expansions from left-to-right in cryptography.
Theor. Comput. Sci., 2005

Left-to-Right Optimal Signed-Binary Representation of a Pair of Integers.
IEEE Trans. Computers, 2005

Implementation and performance analysis of IEEE 802.11i standard using the IXP425 network processor.
Proceedings of the 2nd ACM International Workshop on Performance Evaluation of Wireless Ad Hoc, 2005

Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Cryptanalysis of Shannon-Fano-Elias codes.
Proceedings of the 2005 IEEE International Symposium on Information Theory, 2005

On the signed-binary window method [cryptosystem applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

S-code: new distance-3 MDS array codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

S-Code: new MDS array codes with optimal encoding.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Low-weight left-to-right binary signed-digit representation of N integers.
Proceedings of the 2004 IEEE International Symposium on Information Theory, 2004

A new parallel architecture for low power linear feedback shift registers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Left-to-right binary signed-digit recoding for elliptic curve cryptography.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Attacks and solutions on Aydos-Savas-Koc's wireless authentication protocol.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2003
Low Complexity Multiplication in a Finite Field Using Ring Representation.
IEEE Trans. Computers, 2003

2002
An array based technique for routing messages in distributed double loop networks.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers.
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

1998
Performance based design of high-level language-directed computer architectures.
IEEE Trans. Syst. Man Cybern. Part B, 1998

1997
Nonprime Memory Systems and Error Correction in Address Translation.
IEEE Trans. Computers, 1997

An Iterative Algorithm Using Probabilistic Automata for Predicting the Performance of Parallel Computers.
Proceedings of the Eighth SIAM Conference on Parallel Processing for Scientific Computing, 1997

A Parallel Algorithm to Solve Continuous Time Markov Processes that Model the Performance of Parallel Computers.
Proceedings of the Eighth SIAM Conference on Parallel Processing for Scientific Computing, 1997

1996
An Improvement on Constructions of t-EC/AUED Codes.
IEEE Trans. Computers, 1996

A Note on SEC/AUED Codes.
IEEE Trans. Computers, 1996

A New Residue Arithmetic Error Correction Scheme.
IEEE Trans. Computers, 1996

1995
Comments on "A Systematic (16, 8) Code for Correcting Double Errors and Detecting Triple-Adjacent Errors".
IEEE Trans. Computers, 1995

The Iterative Solution of Lyapunov Equations.
Proceedings of the Seventh SIAM Conference on Parallel Processing for Scientific Computing, 1995

1994
A modified Booth algorithm for high radix fixed-point multiplication.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Comments on "Decomposition of Complex Multipliers Using Polynomial Encoding".
IEEE Trans. Computers, 1994

1989
Information structures in language directed architectures.
Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989


  Loading...