Cristinel Ababei

Orcid: 0000-0002-7609-5304

According to our database1, Cristinel Ababei authored at least 68 papers between 2000 and 2023.

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Bibliography

2023
Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc).
ACM J. Emerg. Technol. Comput. Syst., July, 2023

Can Machine Learning Models be Used to Predict Pollutants based on Measured Other Pollutants?
Proceedings of the IEEE International Conference on Electro Information Technology, 2023

Hardware Description of Event-driven Systems by Translation of UML Statecharts to VHDL.
Proceedings of the IEEE International Conference on Electro Information Technology, 2023

2022
Safeguarding Unmanned Aerial Vehicles Against Side Channel Analysis Via Motor Noise Injection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

Less is More: Learning Simplicity in Datacenter Scheduling.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

Unified Cross-Layer Cluster-Node Scheduling for Heterogeneous Datacenters.
Proceedings of the 13th IEEE International Green and Sustainable Computing Conference, 2022

Performance Evaluation of the Weighted Least Connection Scheduling for Datacenters with BigHouse Simulator.
Proceedings of the 2022 IEEE International Conference on Electro Information Technology, 2022

2021
Quantifying the impact of uncertainty in embedded systems mapping for NoC based architectures.
Microprocess. Microsystems, 2021

Artificial Intelligence Method for the Forecast and Separation of Total and HVAC Loads With Application to Energy Management of Smart and NZE Homes.
IEEE Access, 2021

Sensor Design for Inductive Proximity and Moving Direction Sensing of Metal Targets.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Speeding-Up the Particle Filter Algorithm for Tracking Multiple Targets Using CUDA Programming.
Proceedings of the International Conference on Computational Science and Computational Intelligence, 2021

2020
Using online discussions to connect theory and practice in core engineering undergraduate courses.
Comput. Appl. Eng. Educ., 2020

Reliability Optimization Under Severe Uncertainty for NoC Based Architectures Using an Info-Gap Decision Approach.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Algorithm-Hardware Co-Design in Computing Systems: From Embedded Systems to the Cloud.
Proceedings of the 11th International Green and Sustainable Computing Workshops, 2020

2019
A Survey of Prediction and Classification Techniques in Multicore Processor Systems.
IEEE Trans. Parallel Distributed Syst., 2019

Impact of Uncertainty and Correlations on Mapping of Embedded Systems.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

A Case for Heterogeneous Network-on-Chip Based H.264 Video Decoders.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
Dynamic Energy Optimization in Chip Multiprocessors Using Deep Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018

Dynamic Lifetime Reliability Management for Chip Multiprocessors.
IEEE Trans. Multi Scale Comput. Syst., 2018

Carbon Monoxide Sensing Technologies for Next-Generation Cyber-Physical Systems.
Sensors, 2018

Uncertainty aware mapping of embedded systems for reliability, performance, and energy.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017
Dynamic energy management for chip multi-processors under performance constraints.
Microprocess. Microsystems, 2017

Optimization of patch antennas via multithreaded simulated annealing based design exploration.
J. Comput. Des. Eng., 2017

Performance Evaluation of Network-on-Chip-Based H.264 Video Decoders via Full System Simulation.
IEEE Embed. Syst. Lett., 2017

H.264 video decoder implemented on FPGAs using 3×3 and 2×2 networks-on-chip.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Investigation of LSTM based prediction for dynamic energy management in chip multiprocessors.
Proceedings of the Eighth International Green and Sustainable Computing Conference, 2017

Working on a start-up: A case for an applied entrepreneurship oriented course for senior undergraduates.
Proceedings of the 2017 IEEE Frontiers in Education Conference, 2017

A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016
Open Source Digital Camera on Field Programmable Gate Arrays.
Int. J. Handheld Comput. Res., 2016

Investigation of DVFS for network-on-chip based H.264 video decoders with truly real workload.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016

2015
A new scalable fault tolerant routing algorithm for networks-on-chip.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Investigation of DVFS based dynamic reliability management for chip multiprocessors.
Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

2014
Unified reliability estimation and management of NoC based chip multiprocessors.
Microprocess. Microsystems, 2014

Benefits and costs of prediction based DVFS for NoCs at router level.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

FPGA-based design and implementation of direct torque control for induction machines.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Net reordering and multicommodity flow based global routing for FPGAs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Distributed minimum energy point tracking for systems-on-chip.
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

2013
Dynamic simulation of direct torque control of induction motors with FPGA based accelerators.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012
Secure Comparison Without Explicit XOR
CoRR, 2012

A new reliability evaluation methodology and its application to network-on-chip routers.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Efficient high-speed current-mode links for network-on-chip performance optimization.
Proceedings of the IEEE 25th International SOC Conference, 2012

Unified system level reliability evaluation methodology for multiprocessor Systems-on-Chip.
Proceedings of the 2012 International Green Computing Conference, 2012

2011
Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Energy and reliability oriented mapping for regular Networks-on-Chip.
Proceedings of the NOCS 2011, 2011

A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip.
Proceedings of the IEEE Congress on Evolutionary Computation, 2011

2010
3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans.
Int. J. Reconfigurable Comput., 2010

Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Network on chip design and optimization using specialized influence models.
Proceedings of the 47th Design Automation Conference, 2010

2009
Speeding Up FPGA Placement via Partitioning and Multithreading.
Int. J. Reconfigurable Comput., 2009

A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Achieving network on chip fault tolerance by adaptive remapping.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Parallel placement for FPGAs revisited.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2006
Statistical Analysis and Design of HARP FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Three-dimensional place and route for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Non-contiguous linear placement for reconfigurable fabrics.
Int. J. Embed. Syst., 2006

2005
Timing-driven partitioning-based placement for island style FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Placement and Routing in 3D Integrated Circuits.
IEEE Des. Test Comput., 2005

HARP: hard-wired routing pattern FPGAs.
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

3D FPGAs: placement, routing, and architecture evaluation (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Exploring Potential Benefits of 3D FPGA Integration.
Proceedings of the Field Programmable Logic and Application, 2004

TPR: Three-D Place and Route for FPGAs.
Proceedings of the Field Programmable Logic and Application, 2004

2003
Timing Minimization by Statistical Timing hMetis-based Partitioning.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Placement Method Targeting Predictability Robustness and Performance.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Fast timing-driven partitioning-based placement for island style FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

2002
Multi-objective circuit partitioning for cutsize and path-based delay minimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Statistical Timing Driven Partitioning for VLSI Circuits.
Proceedings of the 2002 Design, 2002

2000
Improving simulation efficiency for circuit-level power estimation [CMOS].
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Probabilistic aspects of crosstalk problems in CMOS ICs.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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