Sudarshan K. Srinivasan

According to our database, Sudarshan K. Srinivasan authored at least 50 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

Rotational abstractions for verification of quantum Fourier transform circuits.

Arun Govindankutty, Sudarshan K. Srinivasan, Nimish Mathure

IET Quantum Commun., 2023

Verification of serialising instructions for security against transient execution attacks.

Kushal K. Ponugoti, Sudarshan K. Srinivasan, Nimish Mathure

IET Comput. Digit. Tech., 2023

Hardware Mitigation and Verification For Rogue In-Flight Data Load Attacks.

Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti, Arun Govindankutty

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022

Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits.

Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith, Nimish Mathure

IET Comput. Digit. Tech., 2022

A Refinement-Based Approach to Spectre Invulnerability Verification.

Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti

IEEE Access, 2022

2021

Formal Verification Approach to Detect Always-On Denial of Service Trojans in Pipelined Circuits.

Kushal K. Ponugoti, Sudarshan K. Srinivasan, Nimish Mathure

Proceedings of the 28th IEEE International Conference on Electronics, 2021

2020

Improved Efficiency of Object Code Verification Using Statically Abstracted Object Code.

N. Shaukat, Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen

Sci. Program., 2020

Formal Verification of Completion-Completeness for NCL Circuits.

Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.

Son N. Le, Sudarshan K. Srinivasan, Scott C. Smith

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Hardware Trojan Design and Detection in Asynchronous NCL Circuits.

Kushal K. Ponugoti, Sudarshan K. Srinivasan, Scott C. Smith

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

A Formal Verification Approach for Detecting Opcode Trojans.

Nimish Mathure, Sudarshan K. Srinivasan, Kushal K. Ponugoti, Akansha Malik, Samuel Quanbeck

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Formal Modeling and Verification of PCHB Asynchronous Circuits.

Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Reliable IoT-Based Embedded Health Care System for Diabetic Patients.

Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman M. Al-Qtiemat, Sana Shuja

CoRR, 2019

An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits.

Mousam Hossain, Ashiq A. Sakib, Sudarshan K. Srinivasan, Scott C. Smith

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

IoT-Based Secure Embedded Scheme for Insulin Pump Data Acquisition and Monitoring.

Zeyad A. Al-Odat, Sudarshan K. Srinivasan, Eman Al-qtiemat, Mohana Asha Latha Dubasi, Sana Shuja

CoRR, 2018

An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits.

Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017

Formal verification methodology for real-time Field Programmable Gate Array.

Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja

IET Comput. Digit. Tech., 2017

Formal modeling and verification for pre-charge half buffer gates and circuits.

Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

2015

A Formal Verification Methodology for DDD Mode Pacemaker Control Programs.

Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen, Dharmakeerthi Nawarathna

J. Electr. Comput. Eng., 2015

A Formal Verification Methodology for FPGA-Based Stepper Motor Control.

Shaista Jabeen, Sudarshan K. Srinivasan, Sana Shuja, Mohana Asha Latha Dubasi

IEEE Embed. Syst. Lett., 2015

2014

Timed Refinement for Verification of Real-Time Object Code Programs.

Mohana Asha Latha Dubasi, Sudarshan K. Srinivasan, Vidura Wijayasekara

Proceedings of the Verified Software: Theories, Tools and Experiments, 2014

Equivalence verification for NULL Convention Logic (NCL) circuits.

Vidura Wijayasekara, Sudarshan K. Srinivasan, Scott C. Smith

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Modeling and Analysis of State-of-the-art VM-based Cloud Management Platforms.

Saif Ur Rehman Malik, Samee U. Khan, Sudarshan K. Srinivasan

IEEE Trans. Cloud Comput., 2013

Equivalence checking for synchronous elastic circuits.

Vidura Wijaysekara, Sudarshan K. Srinivasan

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2012

Refinement-based verification of elastic pipelined systems.

Sudarshan K. Srinivasan, Y. Cai, Koushik Sarker

IET Comput. Digit. Tech., 2012

2011

On the Security of Randomized Arithmetic Codes Against Ciphertext-Only Attacks.

Raj S. Katti, Sudarshan K. Srinivasan, Aida Vosoughi

IEEE Trans. Inf. Forensics Secur., 2011

Desynchronization: design for verification.

Sudarshan K. Srinivasan, Raj S. Katti

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Automatic Refinement Checking of Pipelines with Out-of-Order Execution.

Sudarshan K. Srinivasan

IEEE Trans. Computers, 2010

Optimization Techniques for Verification of Out-of-Order Execution Machines.

Sudarshan K. Srinivasan

J. Electr. Comput. Eng., 2010

Joint optimal placement of PMU and conventional measurements in power systems.

Rajesh Kavasseri, Sudarshan K. Srinivasan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Verifying Pipelines with BAT.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the Design and Verification of Microprocessor Systems for High-Assurance Applications., 2010

2009

Token-Aware Completion Functions for Elastic Processor Verification.

Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti

J. Electr. Comput. Eng., 2009

Verification of Synchronous Elastic Processors.

Sudarshan K. Srinivasan, Koushik Sarker, Rajendra S. Katti

IEEE Embed. Syst. Lett., 2009

Verification of Desynchronized Circuits.

Sudarshan K. Srinivasan, Raj S. Katti

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Efficient Hardware Implementation of a New Pseudo-random Bit Sequence Generator.

Raj S. Katti, Sudarshan K. Srinivasan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A Refinement-Based Compositional Reasoning Framework for Pipelined Machine Verification.

Panagiotis Manolios, Sudarshan K. Srinivasan

IEEE Trans. Very Large Scale Integr. Syst., 2008

Automatic verification of safety and liveness for pipelined machines using WEB refinement.

Panagiotis Manolios, Sudarshan K. Srinivasan

ACM Trans. Design Autom. Electr. Syst., 2008

2007

Efficient Verification of Bit-Level Pipelined Machines Using Refinement.

Sudarshan K. Srinivasan

PhD thesis, 2007

BAT: The Bit-Level Analysis Tool.

Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

2006

A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures.

Panagiotis Manolios, Sudarshan K. Srinivasan

J. Autom. Reason., 2006

Automatic memory reductions for RTL model verification.

Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Monolithic verification of deep pipelines with collapsed flushing.

Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the 3rd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2005), 2005

A complete compositional reasoning framework for the efficient verification of pipelined machines.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Verification of executable pipelined machines with bit-level interfaces.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Refinement Maps for Efficient Verification of Processor Models.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the 2005 Design, 2005

A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements.

Panagiotis Manolios, Sudarshan K. Srinivasan

Proceedings of the 2004 Design, 2004

2003

Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems.

Jun-Cheol Park, Vincent John Mooney III, Sudarshan K. Srinivasan

Microelectron. J., 2003

Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Impress Data-Memory Exceptions.

Sudarshan K. Srinivasan, Miroslav N. Velev

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003